Nan Ya Technology Corporation

Micron Technology Incorporated

Hsin-Chuan Tsai

Pei-Ing Paul Lee

Yi-Nan Chen

Tzung-Han Lee

Neng-Tai Shih

Yinan Chen

Hsu Chiang

Yaw-Wen Hu

Chung-Min Lin

Sheng-Hsiung Wu

Hsien-Wen Liu

Chih-Kun Chen

Yao-Hsiung Kung

Chih-Han Chang

Shan-Chang Wang

Tzu-En He

Chi-Han Chang

A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Methods for forming semiconductor devices

A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Semiconductor device

A method for forming a bottle-shaped trench. A conductive layer surrounded by a doped layer is filled in a lower portion of a trench formed in a substrate. A doping region is formed in the substrate around the doped layer by a heat treatment. A collar silicon nitride layer is formed over an upper portion of the sidewall of the trench. The conductive layer and the doped layer are successively removed using the collar silicon nitride layer as a mask. The doping region is partially oxidized to form a doped oxide region thereon. The doped oxide region is removed to form a bottle-shaped trench. A conformable rugged polysilicon layer is formed in the lower portion of the bottle-shaped trench.

Method for forming bottle-shaped trench

A humidity sensor and fabrication method thereof. In the humidity sensor of the present invention, two comb-type electrodes with a plurality of teeth are disposed on a semiconductor substrate. A SiO sensing film is disposed between the teeth of the two comb-type electrodes on the substrate. A predetermined voltage is applied between the two comb-type electrodes, a leakage current between the two electrodes is detected, and the humidity in the environment is measured according thereto.

Humidity sensor and fabrication method thereof

A chemical mechanical polish apparatus comprises a platen having a polishing pad thereon, a wafer carrier holding a wafer on the polishing pad, and a pusher. The pusher has a base disk and at least two guiding structures at the rim of the base disk. Each guiding structure has a shell with an opening, an elastic device and a pin moving through the opening, wherein the opening is non-linear.

Chemical mechanical polishing apparatus

A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

Method of forming a bottle-shaped trench in a semiconductor substrate

A method for forming shallow trench isolation in an integrated circuit is introduced. Firstly, the first silicon oxide layer and a silicon nitride layer are formed subsequently on the silicon substrate. Then lithography and etching are used to open a shallow trench. Then thermal oxidation is performed. The following step is to form the shallow trench isolation by forming the second silicon oxide with high density plasma enhanced chemical vapor deposition. Then an organic spin-on-glass is coated and low temperature baking is performed. After that, partial etching back is performed to remove spin-on-glass outside the shallow trench. This etching recipe has high selectivity between the second silicon oxide layer to spin-on-glass. Then curing at temperature above 800&deg; C. and etching back are performed with silicon nitride as end point.

Method for forming shallow trench isolation in the integrated circuit

A method of fabricating a horizontal isolation structure between a deep trench capacitor and a vertical transistor thereon is provided. A deep trench capacitor is in the bottom of a deep trench of a substrate. An insulating layer is formed to partially fill the deep trench and also on the substrate by high-density plasma chemical vapor deposition. The insulating layer on the sidewall of the deep trench and on the substrate is removed to transform the insulating layer in the deep trench to an isolation structure. An alternative approach is to form an insulating layer on the substrate and in the deep trench. Then a CMP is performed to remove the insulating layer on the substrate and an etching back is performed to remove the upper portion of the insulating layer in the deep trench. Then the remained insulating layer in the deep trench is served as an isolation structure between the deep trench capacitor and a vertical transistor thereron. The upper portion of the insulating layer in the alternative approach is also can be replaced by a low-cost sacrificial layer.

Method of fabricating an isolation structure between a vertical transistor and a deep trench capacitor

This invention relates to a dual damascene process with porous low-k dielectric material. A first insulating layer is formed on a porous low-k dielectric layer. The first insulating layer has a first pattern for defining a first opening in the low-k dielectric layer. Also, the invention includes the step of forming a second insulating layer on the first insulating layer. Both the first insulating layer and the second insulating layer are used as a hard mask, the two insulating layers being of different materials. The second insulating layer has a second pattern for defining a second opening in the low-k dielectric layer. Then, at least one etch is performed to form a dual damascene structure in the porous low-k dielectric layer by the different insulating layers which cause different protection time in etching the porous low-k dielectric layer.

Dual-damascene process with porous low-K dielectric material

The present invention relates to a method of forming a trench-type capacitor. More particularly, the plate areas of the trench-type capacitor are increased according to the present invention. The method of this invention comprises the steps of: providing a semiconductor substrate; forming a first trench in the semiconductor substrate, wherein the first trench has a first predetermined depth in the semiconductor substrate; forming first spacers on the side-walls of the first trench, wherein the first spacers include second spacers formed at the bottom of the first trench and third spacers exposed to the air; forming a second trench by aligning the semiconductor substrate with masks of the first spacers and etching the semiconductor substrate to a second predetermined depth; forming a first conducting layer by doping ions into the semiconductor substrate in the second trench; forming an oxide layer on the surface of the first conducting layer by oxidation, wherein the thickness of the oxide layer is less than that of the first conducting layer; forming a second conducting layer by removing the oxide layer, removing the first spacers; forming a dielectric layer upon the second conducting layer; and forming a third conducting layer upon the dielectric layer.

Method of forming a trench-type capacitor

A method of making a trench capacitor including the following steps: forming a first trench of predetermined depth into a semiconductor substrate; forming an electrode plate on the side-wall of a bottom of the first trench; forming a dielectric layer on the electrode plate; forming a first conductive portion on the dielectric layer, wherein the first conductive portion fills the bottom of the first trench to form a second trench; forming an insulation layer to fill the bottom portion of the second trench to make a third trench in the second trench; forming a conductive spacer along the side-wall of the third trench; etching the insulation layer using the conductive spacer as a mask to form a forth trench; and then filling the forth trench with a conductive material.

Method of making a trench capacitor

A method of fabricating a stack crown capacitor of a dynamic random access memory (DRAM) cell by using an oxynitride mask is disclosed. First, a dielectric layer and a silicon nitride layer are sequentially deposited over a substrate with an electrical device. Next, forming a contact in the silicon nitride layer and the dielectric layer, and depositing a first polysilicon layer to fill the contact. Next, depositing an oxide layer and an oxynitride layer sequentially, and then defining a bottom electrode pattern for etching the oxynitride layer and the oxide layer. Then, laterally etching the oxide layer, and depositing a second polysilicon layer. Next, etching the second polysilicon layer and the first polysilicon layer by using the oxynitride layer as a mask to form the bottom electrode. Next, removing the oxynitride layer, the oxide layer and partial silicon nitride layer. Finally, forming an interelectrode dielectric layer and a top electrode.

Method of fabricating crown capacitor by using oxynitride mask

A method of rounding the bottom electrode top surface of a stack crown capacitor by using chemical oxidation is disclosed. First, forming a bottom electrode of a stack crown capacitor on a semiconductor substrate. Next, oxidizing the bottom electrode top surface by using oxidant dipping. Finally, removing the oxide from the bottom electrode top surface to achieve the goal of surface planarization. Thereafter, repeating the above steps to meet the requirement of surface planarization.

Method of crown capacitor rounding by oxidant dipping process

A underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition is disclosed. First, a layer of metal pattern is defined on a semiconductor substrate, then a layer of dielectric underlayer is deposited, next, a high O.sub.3 /TEOS interlayer dielectric is formed to achieve planarization. The key point of this process is to apply materials with higher refraction index than conventional PE-TEOS for forming interlayer dielectric underlayer. The mentioned material can be PE-SiH.sub.4 with a constant or decreasing refraction index with the distance from the semiconductor substrate. The underlayer can also be bi-layer structure consisting of high refraction index bottom layer and low refraction index surface layer. This invention can effectively suppress the problem caused from high surface sensitivity of O.sub.3 /TEOS, and improve the quality of interlayer dielectric planarization process dramatically.

Growing community of inventors

Taoyuan, Taiwan

Hsin-Chuan Tsai