United Microelectronics Corp.

Hsin-Chih Yu

Chun-Hsien Huang

Yu-Tse Kuo

Shu-Ru Wang

Chun-Yen Tseng

Ching-Cheng Lung

Li-Ping Huang

Chih-Wei Tsai

Meng-Ping Chuang

Cheng-Tung Huang

Kuo-Chih Lai

Yu-Shu Lin

Po-Cheng Huang

Yu-Wen Wang

Yi-Ting Wu

Ching-I Li

Jen-Yu Wang

Chang-Hung Chen

Po-Chun Yang

Yung-Ching Hsieh

Jian-Jhong Chen

Ya-Jyuan Hung

Shih-Hao Liang

Bo-Chang Li

Ya-Lan Chiou

Yen-Liang Lu

Jhen-Siang Wu

Ting-Hao Chang

Yu-Fang Chen

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Layout of semiconductor memory device

The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Semiconductor layout pattern and forming method thereof

A memory includes (n&#x2212;1) non-volatile cells, (n&#x2212;1) bit lines and a current driving circuit. Each of the (n&#x2212;1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n&#x2212;1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n&#x2212;1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n&#x2212;1) non-volatile cells.

Memory including non-volatile cells and current driving circuit

A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.

Ternary content addressable memory unit capable of reducing charge sharing effect

A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.

Static random access memory

The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

Memory device with oxide semiconductor static random access memory and method for operating the same

A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.

Control circuit used for ternary content-addressable memory with two logic units

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

Manufacturing method for metal gate

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Hsinchu County, Taiwan

Hsin-Chih Yu