Industrial Technology Research Institute

Hsin-Chien Huang

Wen Tsui

Tsung-Yao Chu

Ming Huei Lu

Wei-Chung Lo

Rong-Shen Lee

Enboa Wu

Chung-Tao Chang

Po-Yuan Hsiao

Chu-An Chung

Chi-Chou Chiang

Szu-Wei Lu

Chia-Chung Wang

Jyh-Rong Lin

Fang-Jun Leu

Kuo-Chuan Chen

Hsu-Tien Hu

Chiang-Han Day

Hung-Hsuan Chen

Ruoh-Huey Wang

En-Boa Wu

Randy Hsiao-Yu Lo

Chun-Chia Lai

Yu Cho

An intelligent storage device and an intelligent storage method are provided. The intelligent storage device includes a storage space, an infrared sensor, a weight sensor, a transceiver, and a processor. The storage space is suitable for storing an object. The infrared sensor senses the storage space to generate infrared sensing data. The weight sensor senses the object in the storage space to generate weight sensing data. The processor is coupled to the infrared sensor, the weight sensor, and the transceiver, determines whether the object is placed in or removed from the storage space according to the infrared sensing data and the weight sensing data to generate an event record, and transmits the event record via the transceiver.

Intelligent storage device and intelligent storage method

An intelligent store system and an intelligent store method are provided. The method includes: sensing, by a proximity sensor, whether there is a first customer approaching the proximity sensor; sensing, by an image sensor, a movement trajectory of the first customer; and determining whether the first customer is entering or leaving a store in response to the first customer approaching the proximity sensor sensed by the proximity sensor. If the first customer is entering the store, a first virtual identity and a first virtual shopping cart corresponding to the first virtual identity are generated for the first customer, and a first product list of the first virtual shopping cart is updated according to the movement trajectory. If the first customer is leaving the store, a first operation of the first customer is received by a human machine interface, and the first product list according to the first operation is updated.

Intelligent store system and intelligent store method

A method and a device for analyzing data are provided. The method includes following steps. A plurality of queries for an event stored in a database are integrated to obtain a plurality of features. Each feature is limited at a searching condition. A plurality of items of searched data are obtained from the database according to respective searching condition of each feature. Whether a data volume of the searched data is higher or lower than a predetermined range is determined. If the data volume is higher than the predetermined range, the data volume of the searched data is reduced according to the features. If the data volume is lower than the predetermined range, the data volume of the searched data is increased according to the features. A correlation between the features and the event is analyzed according to the searched data.

Method and device for analyzing data

Provided is a storage method including the following. An object is stored in a storage space. The object is sensed to generate sensing data. An identification model is generated according to the sensing data. In addition, the identification model is uploaded to a server.

Storage device and storage method to identify object using sensing data and identification model

A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.

Method for fabrication of wafer level package incorporating dual compliant layers

A wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads and a method for forming the package. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.

Wafer level package incorporating dual compliant layers and method for fabrication

A single-step bumping/bonding method for forming a semiconductor package of two electronic substrates electrically connected together by solder bumps. In the method, a first electronic substrate is provided equipped with a first plurality of conductive pads formed in an insulating material layer, the plurality of conductive pads each having an aperture formed therethrough for receiving a solder material when the first electronic substrate is positioned juxtaposed to a second electronic substrate equipped with a second plurality of conductive pads such that solder bumps may be formed bonding the first plurality of conductive pads to the second plurality of conductive pads. One of the two electronic substrates may be a silicon wafer, while the other may be a printed circuit board or a silicon wafer.

Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer

A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.

Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication

A method for forming a wafer level package by incorporating an insulating pad of an elastic material under a dummy plug is described. In the method, a multiplicity of pads or islands formed of an elastic material is first formed on a pre-processed semiconductor substrate before a multiplicity of dummy via plugs are formed on top. The dummy via plugs are used as a support structure for building I/O redistribution lines (i.e. metal traces) thereon such that I/O bond pads may be built for supporting solder bumps or solder balls. The multiplicity of insulating pads is used for stress relief during a bonding process with the solder ball built on top without the conventional defect of cracking due to high elasticity of the material when a large area insulating layer is deposited on top. Numerous processing advantages are provided by the present invention method which includes the elimination of direct contact between an elastomeric material layer and a polyimide passivation layer such that potential cracking of the polyamide layer or breaking of I/O redistribution lines can be avoided.

Wafer level package incorporating elastomeric pads in dummy plugs

A method for simultaneous bumping/bonding an IC chip to a semiconductor substrate and a semiconductor package fabricated by the method are described. In the method, a plurality of edge-type conductive pads formed of under-bump-metallurgy layers are first fabricated on an IC chip by dicing through conductive pads formed on a silicon wafer. The edge-type conductive pads, or UBM layer, are then positioned in close proximity to conductive elements formed on a top surface of a semiconductor substrate. A volume of solder is then applied to the interface between the conductive pads and the conductive elements to form electrical bonds between the two. A suitable method for applying the volume of solder may be a solder jetting technique, a solder printing technique or a method utilizing pre-applied solder paste on the surfaces to be bonded together. The present invention method allows a multiplicity of IC chips equipped with edge-type conductive pads to be fabricated by dicing a silicon wafer through conductive pads formed on a top surface. A multiplicity of IC chips can be fabricated at low fabrication cost. The method further provides the benefit that an IC chip may be bonded to a semiconductor substrate in either a face-up or a face-down position. This is made possible by the conductive pads formed on the vertical edges of the IC chip which connect to conductive elements formed on a semiconductor substrate.

Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated

An IC die formed with built-in stress test pattern and a method for forming such pattern are described. The stress test pattern may be formed by first forming a thermal oxide insulation layer on a silicon substrate, then forming a first plurality of diagonally positioned linear metal traces of a first metal, then depositing an electrically insulating material layer on top of the first plurality of diagonally positioned metal traces, and forming a second plurality of L-shaped metal bars of a second metal positioned with the two sides of L parallel to the two sides of a corner region and overlapping the first plurality of metal traces with the electrically insulating material layer therein between. The double metal method for forming the stress test pattern can be easily incorporated into the fabrication process for an IC die without any additional deposition or photolithographic steps. The metal,and metal,layers may be suitably formed of aluminum or an aluminum alloy, or any other conductive metallic material. The L-shaped metal bars formed by the metal,layer should intersect the linear metal traces at a 45&deg; angle with an isolation layer therein between. An electrical resistance between the two metal layers can be determined by a leakage current therein between as a direct indication of the thermo-mechanical stresses, or shear stresses existing between the two metal layers. The present invention stress test pattern can be formed in any size or dimensions as long as one metal layer is formed in linear, diagonal strips while the other metal layer is formed in L-shaped metal bars overlapping the first metal layer.

Built-in stress pattern on IC dies and method of forming

An extended flip chip ball grid array package includes a metal heat slug bonded to the surface of a semiconductor chip. The heat slug has a bonding structure for connecting itself and a BGA substrate panel on which the semiconductor chip is mounted. The heat slug protects the chip from being damaged as well as assists heat dissipation. A first package assembly provides contact bodies on the heat slug for bonding the heat slug to contact pads formed on a BGA substrate panel. A second package assembly fixes the heat slug to a supporting structure bonded on a BGA substrate panel. Supporting stubs are formed on the supporting structure and snapped in openings formed on the contact bodies of the heat slug. Conventional packaging or testing equipment can be used for both package assemblies to manufacture or test the semiconductor chip packages.

Growing community of inventors

Hsinchu, Taiwan

Hsin-Chien Huang