Macronix International Co., Ltd.

Skymedi Corporation

Hsin-Chien Chen

Chun-Hsiung Hung

Yi-Ching Liu

Hsin-Yi Ho

Ming-Hung Chou

Shin-Jang Shen

Ho-Chun Liou

Fuja Shone

I-Long Lee

Fu-Chia Shone

Jen-Ren Huang

Wen-Lin Chang

Gin-Liang Chen

A flash memory includes: a plurality of switches; a global bit line; and a plurality of memory blocks, each containing a plurality of local bit lines, and a plurality of memory units coupled to the plurality of local bit lines respectively. A first switch couples a first local bit line to the global bit line; a second switch couples a second local bit line to the global bit line; a third switch couples the first local bit line to a first voltage source; and a fourth switch couples the second local bit line to a second voltage source.

Flash memory structure

A method for programming a split gate memory cell comprises the following steps. First, a split gate memory cell formed on a semiconductor substrate of a first conductive type, e.g., p-type, is provided. The split gate memory cell has two bitlines of a second conductive type, e.g., n-type, a select gate, a floating gate, a wordline and a dielectric layer deposited between the floating gate and the semiconductor substrate, wherein the select gate and floating gate are transversely disposed between the two bitlines, the wordline is above the select gate and floating gate. Second, a positive voltage is applied to the wordline so as to turn on the floating gate, and a negative voltage is applied to the bitline next to the floating gate, whereby a bias voltage across the tunnel dielectric layer is generated for programming, that is, the so called F-N programming.

Programming and manufacturing method for split gate memory cell

A semiconductor memory device is provided, including one or more bit lines, one or more word lines, and a dummy word line, which is coupled to a positive bias. A memory cell and dummy cell are coupled to a bit line and may be coupled to a word line and dummy word line respectively. Coupling the dummy word line to a positive bias at least during an erase operation prevents the dummy cells from being over-erased, which occurs when the dummy word line is coupled to ground.

Memory device and operation thereof

A NOR-structured semiconductor memory device with a novel configuration of bit line connection is disclosed. The NOR-structured semiconductor memory device comprises a semiconductor memory cell array electrically connected to a plurality of bit lines. The plurality of bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main bit line through at least two bit line transistors, respectively. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively. During a programming or data reading operation, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage or sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device successfully prevents the programming disturbance or correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.

NOR-structured semiconductor memory device

Growing community of inventors

Hsinchu, Taiwan

Hsin-Chien Chen