Dell Products Inc.

Hsin-Chieh Wang

Ching-Lung Chao

Shih-Hao Wang

Hung-Tah Wei

Wei G Liu

Yu-Hsuan Chou

An information handling system includes multiple dual in-line memory modules (DIMMs) and a basic input/output system (BIOS). The DIMMs form a memory system of the information handling system. The BIOS begins a system boot of the information handling system, and performs a first memory reference code training. Based on the first memory reference code training, the BIOS discovers a bad DIMM of the DIMMs, and stores information associated with the bad DIMM. The BIOS reboots the information handling system. During the reboot, the BIOS retrieves the information associated with the bad DIMM. The BIOS disables a slot associated with the bad DIMM. In response to the slot being disabled, the BIOS performs a second memory reference code training. Based on the second memory reference code training, the BIOS downgrades the memory system to a closest possible DIMM population.

Dual in-line memory module map-out in an information handling system

A sub-Non-Uniform Memory Access (sub-NUMA) clustering fault resilient memory system includes an initialization subsystem that is coupled to a processing system and a memory system. The initialization subsystem determines that the processing system and the memory system are configured to provide a plurality of NUMA nodes, allocates a respective portion of the memory system to each of the plurality of NUMA nodes, and configures each respective portion of the memory system to mirror a mirrored subset of that respective portion of the memory system. Subsequently, respective data that is utilized by each of the plurality of NUMA nodes provided by the processing system and the memory system and that is stored in the mirrored subset of the respective portion of the memory system allocated to that NUMA node is mirrored in that respective portion of the memory system.

Sub-NUMA clustering fault resilient memory system

An information handling system includes a plurality of persistent memory devices and a basic input/output system (BIOS). The BIOS begins a power-on self-test (POST) of the information handling system. During the POST, the BIOS may call a block input/output (I/O) driver to access a memory region within the first persistent memory device. The access of the memory region within the first persistent memory device is to determine whether the first persistent memory device is a bootable persistent memory device. The BIOS may determine whether blocks of the memory region contain bad memory locations. In response to the memory region containing bad memory locations, the BIOS may return a device error message without performing the access of the blocks of the memory region within the first persistent memory device and may boot to an operating system of the information handling system via another bootable device.

System and method to prevent endless machine check error of persistent memory devices

A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

System and method to reduce address range scrub execution time in non-volatile dual inline memory modules

An information handling system includes a non-volatile dual in-line memory module (NVDIMM) and a processor. The NVDIMM instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated on the information handling system. The second partition is accessible to the operating system. The first partition includes a first region and a second region. The processor boots the information handling system to configure the NVDIMM based upon information from the first region, detects an error associated with the NVDIMM, and writes information associated with the error to the second region.

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Taoyuan, Taiwan

Hsin-Chieh Wang