Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Epistar Corporation

Hsin-Chieh Huang

Chi-Wen Liu

Ming-Yen Chiu

Ching-Fu Chang

Ching Fu Chang

Hsi-Kuei Cheng

Chih-Kang Han

Chih-Sheng Li

Yu-Wen Wang

Horng-Huei Tseng

Chia-Ming Chang

Cheng-Chien Li

Kuo-Cheng Lee

Yun-Wei Cheng

Chun-Hao Chou

Chao-Hsiung Wang

Yung-Lung Hsu

Tsung-Han Tsai

Ming-Yuan Wu

Che-Lun Chang

Chia-Cheng Chao

Yung-Haw Liaw

Yen-Ming Peng

Che-Yuan Hsu

Yi-Ju Hsu

Chun-Wen Cheng

Chia-Hua Chu

Jiun-Lei Jerry Yu

Yi-Hsien Chang

Jiun-Ming Kuo

Fei-Lung Lai

Ming-Jie Huang

Ming-Cheng Lin

Yu-Syuan Lin

Ji-Yin Tsai

Pin-Chuan Su

Yu-Lin Tsai

Tzu Kai Lin

Chien-Chen Chen

Pao-Ling Kuo

Fu-Sheng Lee

Jiun-Chung Lee

Cheng-Te Chu

Shiao-Shin Cheng

Chen-Shien Chen

Jiann-Tyng Tzeng

Tsung-Shu Lin

Hsing-Kuo Hsia

Chih-Chieh Yeh

Chin-Yu Ku

Kuo-Chio Liu

Hao-Chung Kuo

Wei-Li Huang

Chien-Chia Chiu

Zhen-Yu Li

Yuh-Hwa Chang

Yeh-Jye Wann

De-Dui Liao

Tzu-Min Peng

Tien C Chang

Chung-Pao Lin

Ching-Heng Po

Wen-Yi Wang

Hsi-Shan Kuo

Jheng-Jie Wong

Hsiang-Sheng Su

Tsung-Lung Huang

Che-Yuan Hsu, Deseased

Pei-Ti Yu

Cindy Huichun Shu

Am-Ming Chiang

A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.

Semiconductor devices and methods of manufacturing thereof

A method for fabricating a semiconductor device includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.

A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.

Package with tilted interface between device die and encapsulating material

A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Info structure with copper pillar having reversed profile

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Semiconductor device and method of forming the same

A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

Semiconductor device and manufacturing method thereof

Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Nanostructure and manufacturing method thereof

A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

CMP process and methods thereof

An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.

Package structure and method of forming the same

A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

Semiconductor structure

An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

Integrated fan-out package

A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Fin field-effect transistor device and method

Growing community of inventors

Hsinchu, Taiwan

Hsin-Chieh Huang