Himax Technologies, Inc.

Hsin-Chia Su

Chuan-Che Lee

Jia-Hao Wu

Chin-Tien Chang

A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The timing controller has a plurality of signal output terminals. The source drivers are coupled to the timing controller and the display panel. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, the timing controller outputs a plurality of control packets and a plurality of color data packets to the source drivers. The source drivers respectively output a plurality of pixel voltages corresponding to the color data packets to the display panel according to the corresponding control packets. The training packets, the control packets, and the color data packets are serially transmitted to the source drivers via the signal output terminals.

Display and operating method thereof

A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to one another. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and at least one latch signal to the source drivers based on the lock signal. The source drivers respectively output a plurality of pixel voltages to the display panel according to the latch signal. The training packets and the color data packets are serially transmitted to the source drivers.

A display and an operating method of the display are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to one another. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, the timing controller outputs a plurality of color data packets and a plurality of control packets to the source drivers according to a lock signal. The source drivers respectively output pixel voltages to the display panel and determine output timings of the pixel voltages according to the clock of the timing controller and the control packets. The training packets and the color data packets are serially transmitted to the source drivers.

A voltage generator includes a digital-to-analog (D/A) converting device configured to convert an input voltage to a pair of analog voltages, and a voltage mixer coupled to receive the analog voltages via electrical wirings to combine one or both of the analog voltages into an output voltage.

Voltage generator

A differential charge pump circuit including a common mode bias unit, a first single-ended charge pump unit, and a second single-ended charge pump unit is provided. The common mode bias unit provides a differential signal to a low pass filter. The first single-ended charge pump unit provides a first current to the common mode bias unit or sinks the first current from the common mode bias unit via the first terminal based on an up signal and a down signal. The second single-ended charge pump unit provides a second current to the common mode bias unit or sinks the second current from the common mode bias unit via the second terminal based on the up signal and the down signal. The first and the second single-ended charge pump units respectively charge or discharge the first and the second terminals of the common mode bias unit.

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Tainan, Taiwan

Hsin-Chia Su