Taiwan Semiconductor Manufacturing Comp. Ltd.

Youngtek Electronics Corporation

Hsin-Cheng Chen

Bily Wang

Kuei-Pao Chen

Jack Liu

Sandeep Kumar Goel

Yun-Han Lee

Kai-Yuan Ting

Mei Hsu Wong

Yen-Hao Huang

Jung-Rung Jiang

Ming-Hao Chou

Ren-Chun Ni

Cheng-Chin Chiu

Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.

Function safety and fault management modeling at electrical system level (ESL)

Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.

Active random access memory

A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.

Serialized SRAM access to reduce congestion

A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A static random access memory (SRAM) array is configured to receive each of the plurality of serialized input signals. The SRAM array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.

A packaged chip detection and classification device includes a rotation unit for transporting a plurality of packaged chips, a packaged chip detection unit, and a packaged chip classification unit. The rotation unit includes a rotary turntable, a plurality of receiving portions formed on the rotary turntable, and a plurality of suction-exhaust openings respectively formed in the receiving portions. Each receiving portion is used to selectively receive at least one of the packaged chips. The packaged chip detection unit includes a packaged chip detection module adjacent to the rotation unit for detecting each packaged chip. The packaged chip classification unit includes a packaged chip classification module adjacent to the rotation unit for classifying the packaged chips. Therefore, the packaged chip detection and classification device can be used to detect and classify no-lead packaged chips by matching the rotation unit, the packaged chip detection unit, and the packaged chip classification unit.

Packaged chip detection and classification device

A light-guiding cover structure includes a top cover unit and a light-guiding unit. The top cover unit has a plurality of receiving spaces formed therein. The light-guiding unit includes a plurality of light-guiding groups, wherein each light-guiding group includes a plurality of optical fiber cables received in the corresponding receiving space, and each optical fiber cable has two opposite ends exposed from the bottom surface of the top cover unit and respectively facing at least one light-emitting device and at least one light-sensing device that have been disposed under the top cover unit. Therefore, the optical fiber cables received in the corresponding receiving space, thus when the light-guiding cover structure is applied to the LED package chip classification system, the aspect of the LED package chip classification system can be enhanced.

Light-guiding cover structure

An LED package chip classification system includes a rotation unit for transporting a plurality of LED package chips, a chip test unit, and a chip classification unit. The rotation unit includes a rotary turntable, a plurality of receiving portions formed on the rotary turntable, and a plurality of suction-exhaust dual-purpose openings respectively disposed in the receiving portions. Each LED package chip has a positive electrode pad and a negative electrode pad disposed on the bottom side thereof. The chip test unit includes a chip test module adjacent to the rotation unit for testing each LED package chip. The chip classification unit includes a plurality of chip classification modules adjacent to the rotation unit for classifying the LED package chips. Therefore, the LED package chips can be classified by matching the rotation unit, the chip test unit, and the chip classification unit.

LED package chip classification system

A multi-track detection system for detecting the appearance of electronic elements includes a rotary module, a feeding module, an unvibrated module, a detection module, and a classification module. The rotary module includes a hollow transparent rotary structure having at least two annular guiding areas on the top surface thereof, and the electronic elements are sequentially arranged on the two annular guiding area. The feeding module has two V-shaped feeding grooves for guiding the electronic elements. The unvibrated module includes an unvibrated guiding block having two V-shaped unvibrated guiding grooves respectively communicated with the two V-shaped feeding grooves and respectively corresponding to the two annular guiding areas. The electronic elements on the V-shaped feeding grooves are sequentially transmitted onto the two annular guiding areas through two V-shaped unvibrated guiding grooves, thus each electronic element can be detected by the detection module and classified by the classification module, respectively.

Growing community of inventors

Hsinchu County, Taiwan

Hsin-Cheng Chen