United Microelectronics Corp.

Young Optics Inc.

Hsin-Chang Wu

Neng-Hui Yang

Cheng-Yuan Tsai

Ming-Hua Chang

Tien-Chen Chan

Chun-Yu Chen

Yen-Hsing Chen

Chung-Ting Huang

Shang-Yi Wu

Sheng-Hsu Liu

Chung-Min Tsai

Chieh-Lung Wu

Chih-An Huang

Tsung-Tang Hsieh

Tzu-Chien Chuang

Yu-Wen Fang

Wen-Hsun Lin

The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).

Fin-shaped field effect transistor

A semiconductor device is provided includes a substrate, a gate structure formed on the substrate, an epitaxial source/drain structure respectively formed at two sides of the gate structure, and a boron-rich interface layer. The boron-rich interface layer includes a bottom-and-sidewall portion and a top portion, and the epitaxial source/drain structure is enclosed by the bottom-and-sidewall portion and the top portion.

Semiconductor device

The present invention provides a manufacturing method of a fin-shaped field effect transistor (FinFET), comprises the following steps. Firstly, providing a substrate having a fin structure; forming a gate structure on the fin structure perpendicular to a extending direction of the fin structure; performing an amorphous implantation to form an amorphous layer on a exposed portion of the fin structure exposed by the gate structure and a light-doping implantation; forming a sacrificial spacer on sides of the gate structure covering a portion of the amorphous layer on the fin structure; forming a trench on the fin structure adjacent to the sacrificial spacer; growing an alloy in the trench; and then removing the sacrificial spacer. The invention also provides a FinFET device thereof.

Manufacturing method of a fin-shaped field effect transistor and a device thereof

The present invention discloses a process of manufacturing an STI for avoiding bubble defects, in which, after the shallow trench is formed by etching, substance containing carbon or oxygen on the bottom of the shallow trench is removed, and then the process is continued to accomplish the STI. Alternatively, the removal of substance containing carbon or oxygen may be performed after the oxide liner and the silicon nitride liner are formed on the bottom surface of the shallow trench. The present invention also discloses a process of treating bottom surface of the shallow trench. After the bottom surface of the shallow trench is treated, the bubble defects due to the use of the silicon nitride liner can be avoided.

Process of manufacturing a shallow trench isolation and process of treating bottom surface of the shallow trench for avoiding bubble defects

A laser module including a light emitter, a polarizing and filtering unit, a nonlinear optical crystal, and a first filter is provided. The light emitter emits a first beam. The polarizing and filtering unit is disposed on a transmission path of the first beam. A part of the first beam passes through the polarizing and filtering unit to become a second beam with a specific polarization direction. The nonlinear optical crystal is disposed on a transmission path of the second beam from the polarizing and filtering unit. The nonlinear optical crystal converts a part of the second beam into a third beam. The first filter is disposed on a transmission path of a non-converted part of the second beam and the third beam from the nonlinear optical crystal. The non-converted part of the second beam is reflected by the first filter. The third beam passes through the first filter.

Laser module

A copper damascene process is provided. A semiconductor substrate having a base dielectric layer thereon is prepared. A first damascened copper interconnect structure is formed in the base dielectric layer. The first damascened copper interconnect structure is capped with a dielectric barrier; Subsequently, multiple chemical vapor deposition (CVD) cycles within a CVD reactor is carried out to deposit a low-k dielectric film stack on the first dielectric barrier until thickness of the low-k dielectric film stack reaches a desired value, wherein each of the CVD cycles comprises: (1) chemical vapor depositing a low-k dielectric film having a pre-selected thickness; and (2) cooling down the low-k dielectric film within the CVD reactor. A second damascened copper interconnect structure is formed in the low-k dielectric film stack.

Method of fabricating an interconnect structure having reduced internal stress

A test key formed on a semiconductor substrate has a plurality of electronic components, a plurality of conductors, a plurality of vias for connecting the electronic components and the conductors, a first pad, a second pad, a third pad, and a fourth pad. The first pad, the electronic components, the vias, the conductors, and the second pad connects in series to form a chain circuit, and the first pad and the second pad are positioned at two ends of the chain circuit. A Kelvin structure is composed of the third pad, the fourth pad, one of the conductors, one of the vias, and one of the electronic components.

Test key having a chain circuit and a kelvin structure

A method for forming an adhesion between dielectric layers, it includes forming a first dielectric layer and forming a second dielectric layer having a first portion and a second portion. The first portion is on the first dielectric layer and the second portion is on the first portion. The first portion and second portion are formed by an in-situ method. The first portion has at least one of the following a dielectric constant, hardness or SiCH3/SiO area ratio, which is higher than the second portion. A structure of enhanced-inter-adhesion dielectric layers includes a first dielectric layer and a second dielectric layer having a first portion on the first dielectric layer, and a second portion on the first portion. Herein, the first portion has a dielectric constant around 2.8 to 3.5 higher than second portion.

Method and structure for the adhesion between dielectric layers

A method of enhancing adhesion strength of a boro-silicate glass (BSG) film to a silicon nitride film is provided. A semiconductor substrate with a silicon nitride film formed thereon is provided. The silicon nitride film is then exposed to oxygen-containing plasma such as ozone plasma. A thick BSG film is then deposited onto the treated surface of the silicon nitride film. By pre-treating the silicon nitride film with ozone plasma for about 60 seconds, an increase of near 50% of Kapp of the BSG film is obtained.

Method of enhancing adhesion strength of BSG film to silicon nitride film

A bilayer SiC-based barrier is formed over a metallic wiring layer and a first dielectric layer. The bilayer SiC-based barrier consists of a nitrogen-doped SiC bottom layer and an oxygen-doped SiC top layer. The nitrogen-doped SiC bottom layer has a minimum thickness to prevent metal atoms of the metallic wiring layer from diffusing out to a second dielectric layer and, at the same time, avoid oxygen atoms of the oxygen-doped SiC top layer from diffusing into the metallic wiring layer.

Bilayer silicon carbide based barrier

A pad oxide layer and a silicon nitride (SiN) layer are sequentially formed on a silicon substrate. An etching process is then performed to form a trench in the silicon substrate. A sub-atmospheric chemical vapor deposition (SACVD) process is performed to selectively form a first dielectric layer on exposed portions of the silicon substrate within the trench to fill portions of the trench thereafter. Finally, a high density plasma chemical vapor deposition (HDPCVD) process is performed to form a second dielectric layer to fill the remaining space of the trench and cover the silicon substrate.

Method of forming a shallow trench isolation structure

A method of coating an organic polymeric low-k dielectric layer starts by depositing a protective layer composed of silicon nitride (SiN) or silicon carbide (SiC) on a substrate. A hydrophilic surface is produced across a top surface of the protective layer by performing a fast surface treatment that subjects the surface to an oxygen-containing plasma at a pre-selected low radio frequency power. An adhesion promoter coating layer is formed over the top surface of the protective layer. The coating layer has promoter molecules, each promoter molecule having at least one hydrophobic group and one hydrophilic group. The low-k dielectric layer is spin-on coated onto the coating layer. Formation of the hydrophilic surface alters an orientation of the adhesion promoter molecules to facilitate the hydrophilic group of each of the adhesion promoter molecules facing the hydrophilic surface while the hydrophobic group of the adhesion promoter molecules faces the low-k dielectric layer.

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Hsin-Chu, Taiwan

Hsin-Chang Wu