Via Technologies, Inc.

Mediatek Singapore Pte. Ltd.

Other

Mediatek Corporation

S3 Graphics Co., Ltd.

Hsilin Huang

John Wakefield Brothers

Timour T Paltashev

Boris Prokopenko

Chien-Ping Lu

Kuoyin Weng

Yijung Su

Chao-Chin Chen

Cheng-Ying Ko

Jeff Jiao

Qun-Feng Liao

Qunfeng (Fred) Liao

Hsin-Hao Chung

Chiente Ho

Chienkang Cheng

Joshua Huang

Peng Yu

Xiayang Zhao

Peifeng Wu

Qunfeng Liao

A method, system, and program product accesses chunks of data identifying data elements. A mask is used to identify a position of the data elements that have zero values and that have non-zero values. The data elements are processed based on the mask. For compression of data, data elements in chunks of data that have zero values and that have non-zero values are determined. A mask is used to identify a position of the data elements that have zero values and that have non-zero values. The data elements in the chunks of data having zero values are removed. The data elements having non-zero values are packed into the chunks to form the compressed data. For decompressing the data, zero-value data elements are added in positions in the chunks of data according to the mask to form uncompressed data.

Method, system and program product for mask-based compression of a sparse matrix

A method, system and program product includes examining elements of a first matrix in a sequential fashion. Values of the examined elements are determined. A corresponding bit of a first mask is set to a first value if a determined value is zero. A corresponding bit of a first mask is set to a second value if a determined value is non-zero. The non-zero values are packed in a first vector, wherein bits of at least the first mask determine operations on packed values.

A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a programmable hash function upon at least a portion of the memory address to generate a hashing address; and determining an index of the cache based at least partly on the hashing address.

Method for controlling access of cache through using programmable hashing address and related cache controller

A heterogeneous computing system described herein has an energy-efficient architecture that exploits producer-consumer locality, task parallelism and data parallelism. The heterogeneous computing system includes a task frontend that dispatches tasks and updated tasks from queues for execution based on properties associated with the queues, and execution units that include a first subset acting as producers to execute the tasks and generate the updated tasks, and a second subset acting as consumers to execute the updated tasks. The execution units includes one or more control processors to perform control operations, vector processors to perform vector operations, and accelerators to perform multimedia signal processing operations. The heterogeneous computing system also includes a memory backend containing the queues to store the tasks and the updated tasks for execution by the execution units.

Fine-grained heterogeneous computing

A graphics processing unit (GPU) is provided to preemptively flush one or more bins. The GPU generates bin data of a display area according to an association of primitive data with the bins that correspond to the display area. Upon detecting an adaptive condition, a signal is generated to indicate that one or more bins of a first frame are to be flushed in a first order before the first frame is fully binned. The signal interrupts bin flush of a second frame in a second order in order to flush the one or more bins of the first frame in the first order. After the one or more bins of the first frame are flushed, the bin flush of the second frame is resumed in the second order.

Preemptive flushing of spatial selective bins for deferred graphics processing

An image data processing method is provided. The image data processing method includes the following steps: receiving image data, wherein the image data is in a first pixel format; shuffling the image data according to a relationship between the first pixel format and a second pixel format to generate shuffled data; and compressing the shuffled data by a compression module which is suitable for compressing image data in the second pixel format so as to generate compressed data.

Image data processing method of multi-level shuffles for multi-format pixel and associated apparatus

A multi-hierarchy interconnect system for a cache system having a tag memory and a data memory includes an address interconnect scheduling device and a data interconnect scheduling device. The address interconnect scheduling device performs a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory. The data interconnect scheduling device performs a data bank arbitration to schedule data requests to a plurality of data banks of the data memory. Besides, a multi-hierarchy interconnect method for a cache system having a tag memory and a data memory includes: performing a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory, and performing a data bank arbitration to schedule data requests to a plurality of data banks of the data memory.

Multi-hierarchy interconnect system and method for cache system

A storage system includes a data storage device having a plurality of data storage lines, a tag storage device having a plurality of address tags each associated with one data storage line allocated in the data storage device, and a controller. The controller sets a first number of address tags and configures a first number of data storage lines to serve as a first data storage line with a first data storage line size, and sets a second number of address tags and configures a second number of data storage lines to serve as a second data storage line with a second data storage line size. The second data storage line size is different from the first data storage line size.

Storage system having data storage lines with different data storage line sizes

A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated.

Storage system having tag storage device with multiple tag entries associated with same data storage line for data recycling and related tag storage device

A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.

GPU pipeline synchronization and control system and method

A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that are also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.

Graphics input command stream scheduling method and apparatus

A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register pair, which may be compared to the data in the fence register. If the fence register data is greater than or equal to the wait command associated data, the second module may be acknowledged for sending the wait command and released for processing other graphics operations. If the fence register data is less than the wait command associated data, the second module is stalled until subsequent receipt of a fence command having data that is greater than or equal to the wait command associated data, which may be written to a wait register associated to the addressed register pair.

GPU internal wait/fence synchronization method and apparatus

A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.

GPU pipeline multiple level synchronization controller processor and method

A graphics processing unit ('GPU') is configured to interrupt processing of a first context and to initiate processing of a second context upon command. A command processor communicates an interrupt signal on a communication path from to a plurality of pipeline processing blocks in a graphics pipeline. A token, which corresponds to an end of an interrupted context, is forwarded from the command processor to a first pipeline processing block and subsequently to other pipeline blocks in the graphics pipeline. Each pipeline processing block discards contents of associated memory units upon receipt of the interrupt signal until the token is reached. The token may be forwarded to one or more additional pipeline processing blocks and memory units so that the token is communicated throughout the graphics pipeline to flush data associated with the first context. Data associated with the second context may follow behind the token through graphics pipeline.

Graphics pipeline precise interrupt method and apparatus

A graphics processing unit ('GPU') is configured to interrupt processing of a first context and to initiate processing of a second context upon command so that multiple programs can be executed by the GPU. The CPU creates and the GPU stores a run list containing a plurality of contexts for execution, where each context has a ring buffer of commands and pointers for processing. The GPU initiates processing of a first context in the run list and retrieves memory access commands and pointers referencing data associated with the first context. The GPU's pipeline processes data associated with first context until empty or interrupted. If emptied, the GPU switches to a next context in the run list for processing data associated with that next context. When the last context in the run list is completed, the GPU may switch to another run list containing a new list of contexts for processing.

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Milpitas, CA, United States of America

Hsilin Huang