Nan Ya Technology Corporation

Nayna Technology Corporation

Hsih-Yang Chiu

Wei-Zhong Li

Ting-Cih Kang

Chiang-Lin Shih

Chien-Chung Wang

Pei-Jhen Wu

Ching-Hung Chang

Yi-Jen Lo

Tse-Yao Huang

Yi-Ting Shih

Wei Zhong Li

Chen Chu

The present disclosure provides a method of manufacturing semiconductor chips. The method includes performing a first dry etching process to remove a top metalization layer such that a portion of an interconnect structure is exposed by a scribe line opening after the top metalization layer is removed, wherein the interconnect structure is embedded in a dielectric layer. Next, a first wet etching process using a first etchant is performed to remove a filling layer of the interconnect structure. After performing the first wet etching process, a second wet etching process using a second etchant is performed to remove a glue layer of the interconnect structure. After performing a second wet etching process, a back side stealth dicing process is performed to induce cracks in a substrate from a back side to a front side so as to separate a semiconductor wafer into the semiconductor chips.

Semiconductor chips and method of manufacturing thereof

A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

Semiconductor wafer and testing module

The present application provides a semiconductor structure including a substrate and a conductive member over the substrate. The conductive member includes a seed layer over the substrate, a core disposed over the seed layer, and a protective layer disposed on a top surface of the core and surrounding a sidewall of the core. A method of manufacturing a semiconductor structure is also disclosed.

Semiconductor structure having protective layer on sidewall of conductive member and manufacturing method thereof

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.

Semiconductor device having bonding structure and method of manufacturing the same

A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.

Semiconductor device with selection structure and method for fabricating the same

The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate; disposing a first insulating layer over the semiconductor substrate; disposing a first bottom electrode over the first insulating layer; disposing a first dielectric layer over the first bottom electrode; removing a portion of the first dielectric layer to form a first recess extending through the first dielectric layer; disposing a first capacitor dielectric conformal to the first recess and over the first bottom electrode; and forming a first top electrode within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

Manufacturing method memory device having laterally extending capacitors of different lengths and levels

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an interposer, a conductive via, an insulation layer, and a first electronic component. The interposer has a first surface and a second surface opposite to the first surface. The conductive via extends between the first surface and the second surface of the interposer. The insulation layer separates the conductive via from the interposer. The first electronic component is disposed on the second surface and electrically connected to the conductive via.

Semiconductor device including through-insulator via structure

A method for fabricating a semiconductor device is provided. The method includes providing a substrate; forming a fuse element within the substrate and extending from an upper surface of the substrate; and forming a fuse medium in contact with the fuse element, wherein the fuse medium is spaced apart from the upper surface of the substrate.

Method for fabricating semiconductor device with fuse structure

A method for manufacturing a semiconductor structure is provided. A first mask layer and a photoresist layer are formed over a substrate, wherein photosensitivities of the photoresist layer and the first mask layer are different. A first and a second opening are formed, wherein the first mask layer overlapped by the second opening is degraded to form a second mask layer. The substrate exposed by the first opening is partially removed to form a first recess of the substrate. The second mask layer is removed to form a third opening through the first mask layer. A first dielectric layer is formed, wherein the first dielectric layer fills the first recess and the third opening and covers the substrate overlapped by the third opening. A patterning operation is performed on the substrate using the first dielectric layer as a mask, and a second recess of the substrate is thereby formed.

Method for patterning active areas comprising different operations in semiconductor structure

A semiconductor device is provided. The semiconductor device includes a substrate having an active area and a fuse component. The fuse component has a bottom electrode in the active area, a first dielectric layer on the active area and a top electrode on the first dielectric layer. The semiconductor device also includes a second dielectric layer on the active area and surrounding the first dielectric layer.

Semiconductor device having fuse component

An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.

Integrated circuit package structure with conductive stair structure

A method of forming the electrical fuse matrix includes forming a seed layer on a plurality of bottom metal plates extending in a first direction; forming a plurality of poly-silicon cylinders on the seed layer; forming a spacer surrounding the plurality of poly-silicon cylinders and covering the seed layer; forming a plurality of hourglass-shaped trenches between the poly-silicon cylinders by removing a portion of the spacer; forming a plurality of anti-fuse structures in the hourglass-shaped trenches; and forming a plurality of top metal plates on the anti-fuse structures.

Method of forming electrical fuse matrix

A semiconductor structure includes a substrate, an anti-fuse, first and second transistors, a contact structure, and a dielectric layer. The substrate includes a well region and first and second conductivity type doped regions in the well region, in which the second conductivity type doped region surrounds the first conductivity type doped region and includes a first portion and a second portion perpendicular to the first portion in a top view. The anti-fuse is in an anti-fuse region of the first conductivity type doped region. The first and second transistors are in the well region. The anti-fuse is disposed between the first and second transistors, and the anti-fuse is electrically connected to the first and second transistors. The contact structure is above the anti-fuse. The dielectric layer is between the contact structure and the anti-fuse region of the first conductivity type doped region.

Semiconductor structure

The present application provides a memory device including a semiconductor substrate having a first surface and defined with an active area under the first surface; a gate structure adjacent to the active area and indented into the semiconductor substrate from the first surface; a doped member extending into the semiconductor substrate and surrounded by the active area; a conductive layer including a first portion extending into the semiconductor substrate from the first surface and a second portion disposed over the doped member and coupled to the first portion; and a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active area of the semiconductor substrate, wherein the first portion of the conductive layer is disposed between the gate structure and the doped member. A method of manufacturing the memory device is also disclosed.

Memory device having improved P-N junction and manufacturing method thereof

The present disclosure provides a semiconductor device having an air cavity. The semiconductor device includes a substrate, a first patterned conductive layer, a first dielectric layer, and a second patterned conductive layer. The first patterned conductive layer is on the substrate. The first dielectric layer is on the first patterned conductive layer. The second patterned conductive layer is on the first dielectric layer. The semiconductor device has an air cavity between the first patterned conductive layer and the second patterned conductive layer.

Growing community of inventors

Taoyuan, Taiwan

Hsih-Yang Chiu