Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsien-Wei Chen

Ming-Fa Chen

Jie Chen

Chen-Hua Douglas Yu

Ying-Ju Chen

Der-Chyang Yeh

An-Jhih Su

Hao-Yi Tsai

Shin-Puu Jeng

Tsung-Yuan Yu

Chi-Hsi Wu

Sung-Feng Yeh

Li-Hsien Huang

Wei-Cheng Wu

Wei-Yu Chen

Ching-Jung Yang

Cheng-Hsien Hsieh

Mirng-Ji Lii

Tzuan-Horng Liu

Ming-Da Cheng

Li-Han Hsu

Wen-Hsiung Lu

Yu-Wen Liu

Chih-Chia Hu

Hung-Yi Kuo

Chung-Shi Liu

Tsung-Shu Lin

Shih-Wei Liang

Tung-Liang Shao

Sen-Bor Jan

Tien-Chung Yang

Kai-Chiang Wu

Shih-Hsun Hsu

Chia-Wei Tu

Shang-Yun Hou

Chang-Pin Huang

Hsueh-Chung Chen

Yu-Chia Lai

Ming-Yen Chiu

Hsien-Ming Tu

Tsung-Fu Tsai

Yian-Liang Kuo

Hsiu-Jen Lin

Hsuan-Ting Kuo

Chao-Wen Shih

Chun-Lin Lu

Hung-Jui Kuo

Cheng-Chieh Hsieh

Wen-Chih Chiou

Yu-Feng Chen

Ming-Kai Liu

Chin-Chuan Chang

Chia-Lun Chang

Nien-Fang Wu

Ching-Wen Hsiao

Chun-Hung Lin

Yi-Wen Wu

Meng-Liang Lin

Chao-Hsiang Yang

Shih-Peng Tai

Hua-Wei Tseng

Tsung-Ding Wang

Chia-Lun Tsai

Chien-Hsiun Lee

Jian-Hong Lin

Hsien-Wen Liu

Tzu-Yu Wang

Chuei-Tang Wang

Yen-Ping Wang

Wei-Ting Lin

Ching-Feng Yang

Jyh-Cherng Sheu

Cheng-Ting Chen

Vincent Chen

Chung-Min Fu

Hung-Jen Lin

Yi-Lung Cheng

Chia-Shen Cheng

Kuo-Chuan Liu

Tzu-Wei Chiu

Carlos H Diaz

Kong-Beng Thei

Han-Ping Pu

Cheng-Lin Huang

Ming-Chih Yew

Ta-Pen Guo

Meng-Tse Chen

Pei-Haw Tsao

Kuo-Ji Chen

Hsin-Yu Pan

Hsiang-Ku Shen

Yu-Jen Chen

Harry Hak-Lay Chuang

Chia-Kuei Hsu

Yi-Ming Sheu

Sheng-Chen Chung

Yu-Peng Tsai

Chih-Chiang Tsao

Hung-Jung Tu

Chang-Chia Huang

A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Buffer design for package integration

A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die. The first redistribution circuit structure is disposed on the device die and a first surface of the insulating encapsulant, and the first redistribution circuit structure is electrically connected to the device die.

Package structure

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

Package

Three dimensional structures and methods are provided in which capacitors are formed separately from a first semiconductor device and then connected to the first semiconductor device. For example, a capacitor chip is provided and then bonded to a first semiconductor die. The capacitor chip and the first semiconductor die are encapsulated with a first encapsulant, and one of the capacitor chips and the first semiconductor die are thinned to expose through vias.

Semiconductor devices and methods of manufacture

A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.

Molded dies in semiconductor packages and methods of forming same

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

Packages with metal line crack prevention design

A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.

Semiconductor structures including glass core layer and methods of forming the same

An interposer for a semiconductor package and a method of fabricating an interposer including a peripheral metal pad surrounding an alignment mark. The alignment mark and the surrounding peripheral metal pad are formed on a first dielectric material layer of the interposer. A second dielectric material layer is located over the first dielectric material layer and at least partially over the peripheral metal pad structure and includes an recess extending around a periphery of the alignment mark. A third dielectric material layer is located over the second dielectric material layer and extends into the recess and contacts the alignment mark, the first dielectric material layer, and optionally a portion of the peripheral metal pad. The peripheral metal pad may enhance the adhesion between the first, second and third dielectric material layers near the alignment mark structure and thereby reduce the likelihood of crack formation.

Interposer structure for semiconductor package including peripheral metal pad around alignment mark and methods of fabricating same

A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of the photonic die. In a top-down view, a boundary of the electronic die is within a boundary of the insulating layer, and the boundary of the insulating layer is within a boundary of the photonic die.

Semiconductor structure having photonic die and electronic die

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

Supporting InFO packages to reduce warpage

A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

Method for fabricating a chip package

A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

Semiconductor device and method of manufacture

A semiconductor package includes a first die including an optical coupler, a second die disposed on the first die, and a transparent encapsulation material disposed on the first die. The second die includes a substrate and a transparent portion disposed within the substrate and optically coupled to the optical coupler. The transparent encapsulation material extends along sidewalls of the substrate of the second die.

Semiconductor package

A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor structure includes a stacked die including a lower portion and an upper portion stacked upon the lower portion. The lower portion includes a first patterned conductive pad, a first conductive connector passing through the first patterned conductive pad, a first patterned dielectric layer covering the first patterned conductive pad and laterally isolating the first conductive connector from the first patterned conductive pad. The upper portion includes a second conductive connector bonded to the first conductive connector, and a second patterned dielectric layer bonded to the first patterned dielectric layer.

Semiconductor structure and manufacturing method thereof

Growing community of inventors

Hsinchu, Taiwan

Hsien-Wei Chen