Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsien-Wei Chen

Ming-Fa Chen

Jie Chen

Chen-Hua Douglas Yu

Ying-Ju Chen

Der-Chyang Yeh

An-Jhih Su

Hao-Yi Tsai

Shin-Puu Jeng

Tsung-Yuan Yu

Sung-Feng Yeh

Chi-Hsi Wu

Li-Hsien Huang

Wei-Cheng Wu

Ching-Jung Yang

Wei-Yu Chen

Cheng-Hsien Hsieh

Tzuan-Horng Liu

Mirng-Ji Lii

Ming-Da Cheng

Chih-Chia Hu

Li-Han Hsu

Wen-Hsiung Lu

Yu-Wen Liu

Hung-Yi Kuo

Chung-Shi Liu

Tsung-Shu Lin

Sen-Bor Jan

Shih-Wei Liang

Tung-Liang Shao

Tien-Chung Yang

Kai-Chiang Wu

Shih-Hsun Hsu

Chia-Wei Tu

Shang-Yun Hou

Chang-Pin Huang

Hsueh-Chung Chen

Yu-Chia Lai

Ming-Yen Chiu

Hsien-Ming Tu

Tsung-Fu Tsai

Yian-Liang Kuo

Hsiu-Jen Lin

Hsuan-Ting Kuo

Chao-Wen Shih

Chun-Lin Lu

Wen-Chih Chiou

Hung-Jui Kuo

Cheng-Chieh Hsieh

Yu-Feng Chen

Ming-Kai Liu

Chin-Chuan Chang

Meng-Liang Lin

Chia-Lun Chang

Nien-Fang Wu

Chao-Hsiang Yang

Ching-Wen Hsiao

Chun-Hung Lin

Yi-Wen Wu

Shih-Peng Tai

Hua-Wei Tseng

Tsung-Ding Wang

Chia-Lun Tsai

Chien-Hsiun Lee

Jian-Hong Lin

Hsien-Wen Liu

Tzu-Yu Wang

Chuei-Tang Wang

Yen-Ping Wang

Wei-Ting Lin

Ching-Feng Yang

Jyh-Cherng Sheu

Cheng-Ting Chen

Vincent Chen

Hung-Jen Lin

Chung-Min Fu

Chia-Shen Cheng

Yi-Lung Cheng

Kuo-Chuan Liu

Tzu-Wei Chiu

Carlos H Diaz

Kong-Beng Thei

Han-Ping Pu

Ming-Chih Yew

Cheng-Lin Huang

Ta-Pen Guo

Meng-Tse Chen

Pei-Haw Tsao

Kuo-Ji Chen

Yu-Jen Chen

Hsin-Yu Pan

Hsiang-Ku Shen

Chia-Kuei Hsu

Harry Hak-Lay Chuang

Yi-Ming Sheu

Sheng-Chen Chung

Yu-Peng Tsai

Chih-Chiang Tsao

Hung-Jung Tu

Chang-Chia Huang

A package assembly includes a package substrate including a molding material layer and a plurality of substrate portions embedded in the molding material layer, a redistribution layer (RDL) structure on the package substrate, and a plurality of semiconductor devices on the RDL structure.

Reconstructed substrates for high I/O counts application and methods for forming the same

A semiconductor device includes: a die having die connectors at a front side of the die; a molding material around the die; and a redistribution structure, where the die connectors of the die are attached to a first side of the redistribution structure, where the redistribution structure includes: a dielectric layer; a conductive line extending along a first surface of the dielectric layer facing the die; and a warpage tuning layer contacting and extending along a first surface of the conductive line facing the die, where a first coefficient of thermal expansion (CTE) of the conductive line is smaller than a second CTE of the warpage tuning layer.

Redistribution structure with warpage tuning layer

A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

Bonding structure of dies with dangling bonds

A package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.

Semiconductor packaging and methods of forming same

A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

Method of manufacturing semiconductor devices with system on chip devices

A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

Seal ring for hybrid-bond

A semiconductor structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The second semiconductor die is bonded to the first bonding structure of the first semiconductor die. The first bonding structure includes a first dielectric layer, a second dielectric layer covering the first dielectric layer, and first conductors embedded in the first dielectric layer and the second dielectric layer, wherein each of the first conductors includes a first conductive barrier layer covering the first dielectric layer and a first conductive pillar disposed on the first conductive barrier layer, and the first conductive pillars are in contact with the second dielectric layer.

Semiconductor structure

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Integrated circuit component and package structure having the same

Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Package structure and manufacturing method thereof

A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

3D stacking architecture through TSV and methods forming same

A semiconductor structure includes a first die and a plurality of first dummy pads. The first die includes a first interconnect structure and a first active pad electrically connected to the first interconnect structure. The first dummy pads laterally surround the first active pad and are electrically floating.

A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Buffer design for package integration

A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die. The first redistribution circuit structure is disposed on the device die and a first surface of the insulating encapsulant, and the first redistribution circuit structure is electrically connected to the device die.

Package structure

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

Package

Three dimensional structures and methods are provided in which capacitors are formed separately from a first semiconductor device and then connected to the first semiconductor device. For example, a capacitor chip is provided and then bonded to a first semiconductor die. The capacitor chip and the first semiconductor die are encapsulated with a first encapsulant, and one of the capacitor chips and the first semiconductor die are thinned to expose through vias.

Semiconductor devices and methods of manufacture

Growing community of inventors

Hsinchu, Taiwan

Hsien-Wei Chen