Hannstar Display Corporation

Hannstar Display (nanjing) Corporation

Hsien-Tang Hu

Hsuan-Chen Liu

Chien-Ting Chan

Sung-Chun Lin

Jui-Chi Lai

Chia-Hua Yu

Mu-Kai Kang

Ko-Ruey Jen

Chang-Ming Chao

Ting-Chung Liu

Po-Sheng Shih

Po-Yang Chen

Chung-Lin Chang

Chian-Chih Hsiao

Chien-Hao Wu

Sweehan J H Yang

Kun-Tsai Huang

Yu-Tuan Hsu

Yi-Ting Lee

Po-Yi Chen

Chien-Chih Hsiau

Min-Jung Ho

This invention discloses a display panel including a sub-pixel. The sub-pixel includes a switch device, a first electrode, a transparent electrode, and a reflective electrode. The switch device and the first electrode are disposed in the reflective region and electrically connected. The transparent electrode is disposed on the first electrode and in the reflective region and the light transmissive region. The transparent electrode has a first length in a first direction and a second length in a second direction. The reflective electrode is disposed on the transparent electrode and in the reflective region. The reflective electrode has a third length in the first direction and a fourth length in the second direction, and the third length is greater than the first length, and the fourth length is greater than the second length. The transparent electrode, the reflective electrode, and the first electrode are electrically connected.

Display panel

A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.

Notched display panel

The present invention provides a display panel, the display panel includes at least one first inner sub-pixel disposed in a display region of the display panel and a plurality of first compensation sub-pixels disposed between an end of the first sub-pixel column and the first inner sub-pixel, and a shape of the display region is non-rectangular. Each of the first inner sub-pixel and the first compensation sub-pixels includes a sub-pixel unit, a light shielding sub-block and a color filter block, structures of the sub-pixel units of the first compensation sub-pixels are different from a structure of the sub-pixel unit of the first inner sub-pixel, and the structures of the sub-pixel units of the first compensation sub-pixels are different from each other.

Display panel with non-rectangular display region

A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an mstage scan signal of the 1to Nstage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.

Gate driving circuit and display panel

A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.

Display panel having a test line therein

A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.

Thin film transistor substrate and display device

In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.

Gate driving circuit and display panel with reset function

The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1to Nstage shift registers for respectively generating and sequentially outputting 1to Nstage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1and 2stage shift registers to generate the 1and 2stage scan signals respectively, and the starting signal is utilized to reset the 3to Nstage shift registers.

Gate driving circuit and display apparatus

A display panel is provided, and includes a first substrate, a connecting structure, a passivation layer, a second substrate and a sealant. The first substrate has an active area and a peripheral area. The connecting structure is disposed on the first substrate and located in the peripheral area, and is configured to electrically connect different metal layers. The passivation layer is disposed on and covers the connecting structure. The second substrate is disposed opposite to the first substrate. The sealant is sandwiched between the first substrate and the second substrate. In the display panel, a vertical projection of the sealant on the first substrate and a vertical projection of the connecting structure on the first substrate are overlapped.

Display panel and method of fabricating the same

A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.

Semiconductor device and manufacturing method thereof

A pixel substrate and a fabrication method thereof are provided. The method includes: forming a gate and a lower pad on a substrate; forming a gate insulating layer overlaying the gate and the lower pad; forming a channel layer and a first electrode layer on the gate insulating layer, in which the projection areas of the channel layer and the gate on the substrate are overlapped; forming an etching-barrier material layer on the substrate and simultaneously forming a contact opening at the gate insulating layer to expose the lower pad; forming a source, a drain and an upper pad on the substrate; forming a protective layer; forming a second electrode layer with multiple slits on the protective layer, in which one of the first and second electrode layers is electrically connected to the drain. The invention can simplify the process steps and reduce fabrication time.

Pixel substrate and fabrication method thereof

A pixel structure of a liquid crystal display panel includes a first substrate; a color filter layer formed on the first substrate, the color filter layer comprising a plurality of filtering areas for filtering light, and a plurality of blocking areas for blocking light; a main spacer formed on one of the blocking areas; a sub spacer formed on another one of the blocking areas; a second substrate; a thin film transistor formed on the second substrate; an insulating layer formed above the thin film transistor and the second substrate; a liquid crystal layer formed between the first substrate and the second substrate; wherein a distance from an upper surface of the insulating layer near the main spacer to the second substrate is greater than a distance from an upper surface of the insulating layer near the sub spacer to the second substrate.

Pixel structure of a liquid crystal display panel and pixel forming method thereof

The pixel structure includes a scan line, a data line, a thin-film transistor, a first electrode layer, a protective layer and a second electrode layer. The thin-film transistor is electrically connected to the scan line and the data line, and includes a gate, an oxide semiconductor layer, an insulating layer, a source and a drain. The first electrode layer is in the same layer as the oxide semiconductor layer, and is surrounded by the scan line and the data line. The second electrode layer is located on the first electrode layer, and the protective layer is located between the first electrode layer and the second electrode layer, wherein one of the first and second electrode layers is electrically connected to the thin-film transistor, and the other is connected to a common voltage. The second electrode layer includes a plurality of slits exposing an area of the first electrode layer.

Pixel structure and fabricating method thereof

A transflective type liquid crystal display comprises a first substrate with a reflective region and a transmission region. A gate region, an insulation layer and a semiconductor layer are sequentially formed on the first substrate. The semiconductor layer has a source region, a drain region and a channel region. A first dielectric layer is disposed on the semiconductor layer and has a through hole to expose a part of the drain region. A first common electrode is disposed on the first dielectric layer and the through hole to cover the exposed part of the drain region. A reflective electrode is disposed on the first dielectric layer located in the reflective region. A second dielectric layer is disposed on the first common electrode and the reflective electrode. A pixel electrode is disposed on the second dielectric layer and connected to the drain region via the through hole.

Transflective liquid crystal display and method thereof

A method for manufacturing a transflective liquid crystal display panel includes providing an array substrate having a plurality of pixel regions, each of the pixel regions includes a device region, a transmission region and a reflection region defined therein; forming a first metal layer on the array substrate; patterning the first metal layer to simultaneously form a gate electrode in the device region and a plurality of metal bumps in the reflection region; forming a first insulating layer having a rough surface and covering the gate electrode and the metal bumps on the array substrate; forming a patterned semiconductor layer on the gate electrode; forming a reflective layer covering the first insulating layer and having a rough surface in the reflection region; and sequentially forming a patterned second insulating layer and a transparent pixel electrode on the array substrate.

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Taichung, Taiwan

Hsien-Tang Hu