Etron Technology, Inc.

Mediatek Corporation

Hsien-Sheng Huang

Chun Shiah

Yu-Hsuan Lin

Gyh-Bin Wang

Tsung-Han Wu

Shou-En Liu

Feng-Chia Chang

Chun-Peng Wu

Ching-Gu Pan

Chen-Yuan Chang

Ming-Tsung Lin

An interface circuit of an electronic device includes one or more pins, an internal circuit, an over-voltage protection circuit and a monitoring circuit. The pins are selectively connected to an external circuit. The over-voltage protection circuit is coupled between the internal circuit and at least one pin to prevent the internal circuit from being damaged by a voltage spike or a current surge received at the pin. The monitoring circuit is configured to monitor one or more electrical characteristics of at least one critical component in the internal circuit or the over-voltage protection circuit by monitoring the value of at least one parameter related to the electrical characteristics of the critical component. When the value of the parameter is outside of a safety range, the monitoring circuit outputs a warning signal.

Interface circuits to monitor and prevent overstress damage

A system using a USB Type-C interface is provided. This system not only transmits the normal USB signal but also supports a DisplayPort Alternate Mode. Moreover, due to the novel pin arrangement of the multi-function control circuit, the cost of the overall system is reduced, and the area of the printed circuit board is effectively reduced.

System and circuit using USB Type-C interface

A delay-locked loop (DLL) circuit. In the evaluation period, the DLL circuit adjusts needed delay period of time for a reference clock signal by adjusting the amount of the used delay units which each of has fixed delay period of time digitally and controlling the delay period of time of the voltage control delay circuit analogically. In the locking period, the DLL circuit utilizes the delay time of the delay units, which is decided in the evaluation period, along with the voltage control delay circuit, to lock phase of the reference clock signal. In this way, the stability of the delay period of time of the voltage control delay circuit increases.

DLL circuit with wide-frequency locking range and error-locking-avoiding function

A DLL with power-saving function includes a VCDL, a voltage control module, a capacitor, and a phase detector. The VCDL generates a delayed clock signal according to the voltage on the capacitor and a reference clock signal. The phase detector detects phase difference between the delayed clock signal and the reference clock signal and accordingly controls the voltage controller. The voltage controller sinks or sources current to the capacitor for adjusting the voltage on the capacitor. Further, the voltage controller can turn off its charge pump according to a turned-off signal and stops sinking or sourcing current for saving power.

Delayed-locked loop with power-saving function

The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream, which comprises N parallel signals divided into a first group of parallel signals and a second group of parallel signals, to be in accordance with a first sequence of N sampling pulses, and a sampling module sequentially samples each signal in the first group signals and the second group signals with the N sampling pulses in a second sequence and outputs a serial signal.

Method and circuit for transferring data stream across multiple clock domains

The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.

Low voltage differential signal receiver

A duty cycle correction circuit with wide-frequency working range utilizes a pulse generator having adjustable pulse width function to adjust the width of the pulse and outputs a clock signal with the duty cycle of 50%. The pulse generator includes a NAND gate, a modulation device, and an inverter. The inverter is coupled between the second input end of the NAND gate and the modulation device. The modulation device modulates the low-level status of the input clock signal and accordingly outputs to the inverter. The first input end of the NAND gate receives the input clock signal. The NAND gate operates NAND calculation to the signals received on the input ends of the NAND gate and accordingly outputs a periodic low-level pulse signal.

Duty cycle correction circuit with wide-frequency working range

PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

Phase/frequency detector

A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum.

Spread spectrum clock generator

A duty cycle correction circuit comprises a tuned circuit, a delay circuit and a phase-locked loop; wherein the tuned circuit receives an input clock, generates a periodic pulse according to the input clock, tunes the periodic pulse depending on a reference voltage, and outputs an output clock; a delay circuit receives the output clock, and generates a complementary signal; a phase lock loop receives the complementary signal, measures the periods of time of the high level state and the low level state of the complementary signal, generates the reference voltage and feeds back to the tuned circuit. By using the technique of the present invention, it is able to track the delay time between the input clock and the output clock, and the drift of the output clock is reduced.

Duty cycle correction circuit

An inverter with adjustable threshold and irrelative to voltage, temperature, and process is disclosed. The inverter includes an input end for receiving an input signal; an output end for outputting an inverted signal of the input signal; a first PMOS whose gate is coupled to the input end, drain is coupled to the output end, and the source is coupled to a power supply; a first NMOS whose gate is coupled to the input end, drain is coupled to the output end, and source is coupled to a ground end, and an adjustable current source coupled to the output end for providing current with adjustable size to the output end for adjusting threshold of the inverter.

Growing community of inventors

Hsinchu, Taiwan

Hsien-Sheng Huang