National Taiwan University

Intel Corporation

National Applied Research Laboratories

Hsien-Ku Chen

Shey-Shi Lu

Pei-Wei Chen

Ying-Zong Juang

Chin-Fong Chiu

Da-Chiang Chang

Fang-Ren Liao

Bing-Jye Kuo

The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.

DC bias circuit and the radio frequency receiver circuit using the same

The present invention presents a RF receiver circuit including an inductor-coupling single-ended input differential-output LNA, a mixer circuit, and a differential trans-impedance amplifier. The inductor-coupling single-ended input differential-output LNA includes a single-ended input, a balance-to-unbalance transformer, and an inductor-less differential LNA. The balance-to-unbalance transformer is used to transform the radio frequency signals into a plurality of differential-output first differential signals and includes a first inductor and a second inductor. The inductor-less differential LNA is used to transform the first differential signals into a plurality of differential-output second differential signals, wherein the input impedance of the inductor-coupling single-ended input differential-output LNA is inversely proportional to the square of the coil ratio of the first and second inductor, and the product of the reciprocal of the coil ratio and the input impedance matches the external input impedance of the inductor-coupling single-ended input differential-output LNA.

Radio frequency receiver circuit and the inductor-coupling single-ended input differential-output low-noise amplifier thereof

A frequency detection circuit includes a filter, a power detector and a voltage comparator. The filter receives and filters a converted signal to generate a filtered signal. The power of the filtered signal relates to a frequency of the converted signal. The power detector generates a voltage according to the power of the filtered signal. The voltage comparator compares the voltage with multiple reference voltages to generate multiple comparison results. At least one of the inductance and capacitance of an LC tank in an amplifier is adjusted according to the comparison results.

Frequency detection circuits, radio frequency signal processing devices and methods for calibrating inductance and capacitance

A dual mode RF transceiver is provided. The dual mode RF transceiver comprises an antenna, a differential low noise amplifier (LNA), a local oscillator and a dual mode differential mixer. The differential LNA receives an RF signal from the antenna to generate a differential amplified RF signal. The dual mode differential mixer comprises a switch module, a plurality of fundamental mixers and a plurality of sub-harmonic mixers. The fundamental mixers are activated in a first receiving mode to generate a first differential baseband signal according to a multiphase local oscillating (LO) signal from the local oscillator and the differential amplified RF signal. The sub-harmonic mixers are activated in a second receiving mode to generate a second differential baseband signal according to the multiphase LO signal from the local oscillator and the differential amplified RF signal. An RF signal receiving method is disclosed herein as well.

Dual mode RF transceiver and receiving method of the same

The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Phase-locked loop circuit and an associated method

This invention provides a voltage-controlled oscillator, comprising a first voltage-controlled oscillator circuit and a second voltage-controlled oscillator circuit. The first voltage-controlled oscillator circuit comprises a plurality of inductors, a plurality of variable capacitors, and a plurality of MOS transistors. The circuit configuration of the second voltage-controlled oscillator circuit is symmetrical to that of the first voltage-controlled oscillator circuit. The inductors of the first voltage-controlled oscillator circuit are cross-coupled to the inductors of the second voltage-controlled oscillator circuit.

Voltage-controlled oscillator

The invention includes a harmonic suppression circuit, an injection-locked frequency divider circuit (ILFD) and associated methods. The harmonic suppression circuit comprises a source voltage, two suppression modules, two input terminals, two smoothed output terminals and a ground. The ILFD comprises a ground, an input transistor, an input terminal, two divider legs, two output terminals and a source voltage. The associated method to improve harmonic suppression comprises acts of synthesizing differential-phase signals and simultaneously suppressing second harmonics of in-phase signals. The method to extent an ILFD's locking range comprises acts of decreasing quality factor while keeping resonance frequency constant.

Harmonic suppression circuit, an injection-locked frequency divider circuit and associated methods

A multimode millimeter-wave frequency divider circuit with multiple selectable frequency dividing modes is proposed, which is designed for integration with a millimeter wave (MMW) circuit system, such as a phase-locked loop (PLL) circuit, for providing multimode frequency dividing functions. In actual application, the millimeter wave frequency divider circuit of multi frequency dividing mode provides at least three frequency dividing operational modes, including modes of dividing two, dividing 3 and dividing four. In practice, the millimeter wave frequency divider circuit of multi frequency divider mode may be integrated with a millimeter wave phase-locked circuit to provide a frequency synthetic function having multi frequency sections, such as including 38 GHZ, 60 GHZ and 77 GHZ, and may use reduced circuit layout surfaces and operational power.

Multimode millimeter-wave frequency divider circuit with multiple presettable frequency dividing modes

An adapter for RF front end processor chip wherein the RF front end processor chip includes a low noise amplifier which is used to receive a RF filter signal so as to generate a first signal. An adapter is used to receive a first signal so as to induce and generate a second signal and a third signal which is electrically reverse. Then a frequency mixer of the RF front end processor chip is used to receive the second signal and the third signal and a resonant signal, the second signal and the third signal are used to generate a medium frequency signal. Wherein, adapter includes a primary measured coil.

Adapter for the RF front end processor chip

A wideband low noise amplifier. The wideband low noise amplifier comprises an amplifier, an output device, and an inductor. The amplifier amplifies an input signal received from an input node, and outputs the amplified signal to an output node. The output device is coupled to a first voltage and the output node. The peaking inductor is coupled between the amplifier and the output device.

Growing community of inventors

Taipei, Taiwan

Hsien-Ku Chen