Intel Corporation

Hsien-Hsin Lee

Vladimir M Pentkovski

Hsien-Cheng Emile Hsieh

Subramaniam M Maiyuran

Niranjan L Cooray

Salvador Palanca

Deep K Buch

Michael K Dwyer

Angad Narang

Jagannath Keshava

Steve Tsai

Praveen B Mosur

Suresh N Kuttuva

Steve Spangler

A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.

Method and apparatus for prefetching data into cache

The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M vertex coordinates corresponding entirely to the N polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.

Processing polygon meshes using mesh pool window

The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.

Efficient utilization of write-combining buffers

The present invention discloses a method and apparatus for processing strips of data, each strip referencing a plurality of parameter sets stored in a memory. The method comprises: prefetching a plurality of parameter sets referenced in a first strip; performing an operation on each of the prefetched parameter sets; and concatenating a first strip and a second strip to eliminate a memory access latency in the second strip.

Pipelined processing of short data streams using data prefetching

Growing community of inventors

El Dorado Hills, CA, United States of America

Hsien-Hsin Lee