Microjet Technology Company, Ltd.

Hsien-Chung Tai

Chi-Feng Huang

Yung-Lung Han

Hao-Jan Mou

Ying-Lun Chang

Wen-Hsiung Liao

Rong-Ho Yu

Cheng-Ming Chang

Chang-Yen Tsai

Chun-Yi Kuo

Wei-Ming Lee

Tsung-I Lin

Chin-Wen Hsieh

Lin-Huei Fang

Ta-Wei Hsueh

Hsuan-Kai Chen

Chin-Chuan Wu

Kwo-Yuan Shi

Yang Ku

Ke-Ming Huang

Chiang-Ho Cheng

Wen-Ti Lo

A nasal-plug filter device including a device body, a filter, a first actuator, a second actuator, and a gas sensor is provided. The device body has a ventilating channel, and the ventilating channel has an inlet end and an outlet end. The filter is disposed at the outlet end. The first actuator is disposed at the inlet end for being driven to transmit gas outside the device body into the device body. The second actuator is stacked on and bonded to the first actuator, and the second actuator is driven to transmit the gas transmitted by the first actuator to the filter to be filtered and purified. The gas sensor is disposed at the outlet end for detecting a gas quality of the gas at the outlet end. A connection element may be provided for connecting two nasal-plug filter devices with each other.

Nasal-plug filter device

A heterogeneous integration chip of a micro fluid actuator is disclosed and includes a first substrate, a first insulation layer, a first conductive layer, a piezoelectric layer, a second conductive layer, a second substrate, a control element, a perforated trench and a conductor. The first substrate includes a first chamber. The first insulation layer is disposed on the first substrate. The first conductive layer is disposed on the first insulation layer and includes an electrode pad. The piezoelectric layer and the second conductive layer are stacked on the first conductive layer sequentially. The second substrate is assembled to the first substrate through a bonding layer to define a second chamber and includes an orifice, a fluid flowing channel and a third chamber. The control element is disposed in the second substrate. The perforated trench filled with the conductor is penetrated from the electrode pad to the second substrate.

Heterogeneous integration chip of micro fluid actuator

The method of the present disclosure includes steps of: (S1) providing a silicon substrate; (S2) arranging and disposing an active component layer by utilizing a first type photomask on at least two high-precision regions of each of a plurality of inkjet print head chip regions on the silicon substrate; (S3) arranging and disposing a passive component layer by utilizing a second type photomask on the active component layer; and (S4) cutting the silicon substrate according to the inkjet print head chip regions so as to form the plurality of narrow type inkjet print head chips.

Manufacturing method of narrow type inkjet print head chip

A manufacturing method of miniature fluid actuator is disclosed and includes the following steps. A flow-channel main body manufactured by a CMOS process is provided, and an actuating unit is formed by a deposition process, a photolithography process and an etching process. Then, at least one flow channel is formed by etching, and a vibration layer and a central through hole are formed by a photolithography process and an etching process. After that, an orifice layer is provided to form at least one outflow opening by an etching process, and then a chamber is formed by rolling a dry film material on the orifice layer. Finally, the orifice layer and the flow-channel main body are flip-chip aligned and hot-pressed, and then the miniature fluid actuator is obtained by a flip-chip alignment process and a hot pressing process.

Manufacturing method of miniature fluid actuator

A miniature fluid actuator is disclosed and includes a substrate, a chamber layer, a carrying layer and a piezoelectric assembly. The substrate has an inlet. The chamber layer is formed on the substrate and includes a first chamber in communication with the inlet, a resonance layer and a second chamber. The resonance layer has a central aperture in communication between the first chamber and the second chamber. The carrying layer includes a fixed region formed on the chamber layer, a vibration region, a connection portion and a vacant. The vibration region is located at a center of the fixed region and corresponding to the second chamber. The connection portion is connected between the fixed region and the vibration region. The vacant is formed among the fixed region, the vibration region and the connection portion. The piezoelectric assembly is formed on the vibration region.

Miniature fluid actuator

A wafer structure is disclosed and includes a chip substrate and an inkjet chip. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the inkjet chip. The inkjet chip includes plural ink-drop generators generated by the semiconductor process on the chip substrate. Each of the plurality of ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and plural horizontal axis array groups having a central stepped pitch equal to or less than 1/600 inches.

Wafer structure

A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500&#x2dc;5000 angstroms, the protective layer has a thickness of 150&#x2dc;3500 angstroms, the resistance heating layer has a thickness of 100&#x2dc;500 angstroms, the resistance heating layer has a length of 5&#x2dc;30 microns, and the resistance heating layer has a width of 5&#x2dc;10 microns.

A wafer structure including a chip substrate and plural inkjet chips is disclosed. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of at least 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the first inkjet chip and the second inkjet chip. Each of the first inkjet chip and the second inkjet chip includes plural ink-drop generators. Each of the ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and form plural horizontal axis array groups having a central stepped pitch equal to 1/600 inches or less.

A wafer structure is disclosed and includes a chip substrate and plural inkjet chips having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500&#x2dc;5000 angstroms, the protective layer has a thickness of 150&#x2dc;3500 angstroms, the resistance heating layer has a thickness of 100&#x2dc;500 angstroms, the resistance heating layer has a length of 5&#x2dc;30 microns, and the resistance heating layer has a width of 5&#x2dc;10 microns.

A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate fabricated by a semiconductor process. At least one inkjet chip is directly formed on the chip substrate by the semiconductor process and diced into the at least one inkjet chip for inkjet printing. Each of the inkjet chip includes a plurality of ink-drop generators produced by a semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle.

A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip. The chip substrate is a silicon substrate fabricated by a semiconductor process. The inkjet chip is directly formed on the chip substrate by the semiconductor process, whereby the wafer structure is diced, and the inkjet chip is produced, to be implemented for inkjet printing. The inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a barrier layer, an ink-supply chamber and a nozzle, and the ink-supply chamber and the nozzle are integrally formed in the barrier layer.

A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of at least 12 inches. The inkjet chips include at least one first inkjet chip and at least one second inkjet chip directly formed on the chip substrate by the semiconductor process, respectively, and the plurality of inkjet chips are diced into the at least one first inkjet chip and the at least one second inkjet chip for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by a semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle.

A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The at least one inkjet chip is directly formed on the chip substrate by the semiconductor process, and the wafer is diced into the at least one inkjet chip, to be implemented for inkjet printing.

A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate. Each ink-drop generator includes a barrier layer, an ink-supply chamber and a nozzle. The ink-supply chamber and the nozzle are integrally formed in the barrier layer.

A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing.

Growing community of inventors

Hsinchu, Taiwan

Hsien-Chung Tai