Nan Ya Printed Circuit Board Corporation

Nan Ya Pcb Corp.

Nan Ya Printed Circuit Bored Corporation

Hsien-Chieh Lin

Shing-Fun Ho

Kuo-Chun Chiang

Shih-Tsung Lin

Tung-Yu Chang

Hsing-Lun Lo

Cheng-Hung Huang

Chih-Chung Chu

A method of fabricating a circuit board structure is provided. The method includes providing a core substrate; forming an insulation layer on the core substrate; forming a patterned metal layer on the insulation layer, wherein the patterned metal layer includes a wiring layer and a pad; forming a first metal pillar on the pad, wherein the first metal pillar has a top surface; and forming a first solder resist layer on the patterned metal layer and the first metal pillar, wherein the first solder resist layer has a first opening exposing the first metal pillar, and the first opening has a bottom surface, wherein the top surface of the metal pillar is higher than or equal to the bottom surface of the first opening.

Circuit board structures and methods of fabricating the same

The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.

Printed circuit board and method for fabricating the same

The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.

Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.

Printed circuit board structure

A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.

Lot traceable printed circuit board

A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.

Embedded chip package with improved heat dissipation performance and method of making the same

A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of the first metal layer is disposed on the insulating layer. A pillar-shaped second metal layer is disposed within the opening directly on the first metal layer. A solder ball filled into the opening is in contact with the pillar-shaped second metal layer.

Growing community of inventors

Taoyuan County, Taiwan

Hsien-Chieh Lin