Industrial Technology Research Institute

Hsien-Chie Cheng

Su-Tsai Lu

Yun-Chiao Chen

Wen-Hwa Chen

Shyh-Ming Chang

Ji-Cheng Lin

Yao-Sheng Lin

Tai-Hong Chen

Yung-Yu Hsu

Cheng-Ta Pan

Zi-Hao Ye

Kuo-Ning Chiang

Chang-An Yuan

Kung-Chieh Huang

Chang-Chun Lee

A circuit board includes a substrate and at least one circuit structure. The substrate has first slots, each first slot extends along a first axis, and a length of each first slot along the first axis is greater than lengths of each first slot along other directions. The circuit structure is disposed on the substrate and includes arc segments and extending segments. Each arc segment is connected between two of the extending segments such that the circuit structure is circuitous. The circuit structure and each first slot have an interval therebetween such that each first slot and a part of a surface of the substrate are exposed by the circuit structure. Each first slot is located between adjacent two extending segments, and the first axis of each first slot passes through the corresponding arc segment. In addition, an electronic device having the circuit board is also provided.

Circuit board and electronic device

In order to avoid the capacitors in a stacked capacitor structure suiting a miniaturization process from collapsing to cause a short-circuit, separated reinforced structures are used and disposed at the outer-sidewalls of the capacitor, which not only reduces the space occupied by the reinforced structure to increase the surface areas of the upper electrode and the lower electrode of the capacitor, but also allows the capacitor to be deflected but collapse-proof and there are more spaces between the capacitors, so as to solve the filling difficulty problem due to a too small filling space in a successive process of depositing conductive material into the filling space.

Stacked capacitor structure and manufacturing method thereof

After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.

Electrode structure of memory capacitor

A composite bump suitable for disposing on a substrate pad is provided. The composite bump includes a compliant body and an outer conductive layer. The coefficient of thermal expansion (CTE) of the compliant body is between 5 ppm/&#xb0; C. and 200 ppm/&#xb0; C. The outer conductive layer covers the compliant body and is electrically connected to the pad. The compliant body can provide a stress buffering effect for a bonding operation. Furthermore, by setting of the CTE of the compliant body within a preferable range, damages caused by thermal stress are reduced while the bonding effect is enhanced.

Composite bump

The present invention relates to a three-dimensional multichip stack electronic package structure and method for making the same, including a main substrate having at least a pin-hole set and at least a flexible substrate having at least a pin terminal. At least an electronic device including an active component and a passive component is attached to the flexible substrate by adhesion. In the flexible substrate, electric signals of the electronic device are delivered to the pin terminal through at least a conductive wire for transmitting electric signals. In assembly, the pin terminal of the flexible substrate is inserted into the pin hole of the main substrate. Then, the flexible substrate is folded so as to package the electronic device in a three-dimensional multichip stack manner.

Three-dimensional multichip stack electronic package structure

Growing community of inventors

Hsinchu, Taiwan

Hsien-Chie Cheng