Intel Corporation

Hsien-Cheng Emile Hsieh

Vladimir M Pentkovski

Shreekant S Thakkar

Thomas R Huff

Patrice L Roussel

Mohammad A F Abdallah

Hsien-Hsin Lee

Subramaniam M Maiyuran

Mohammad A Abdallah

Lance E Hacking

Deep K Buch

Michael K Dwyer

Hsin-Chu Tsai

Mohammad Af Abdallah

A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.

Method and apparatus for performing cache segment flush and cache segment invalidation operations

A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.

Method and apparatus for processing 2D operations in a tiled graphics architecture

A method and apparatus for efficient parametric surface binning based on control points. One method of the present invention comprises transforming control points for a parametric surface. An extent of the control points is determined. Tiles interested by the extent are determined. The parametric surface is stored into the tiles.

Efficient parametric surface binning based on control points

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

Method and apparatus for ensuring backward compatibility in a bucket rendering system

The present invention discloses a method and apparatus for optimizing three-dimensional (3-D) transformation on N vertices of a data object based on a transformation matrix of size K&times;K. The method comprises: storing coordinates of the N vertices in K data items, each of the K data items having N elements; and scheduling a sequence of M operations with a set of P storage elements, the sequence of M operations performing a matrix multiplication of the transformation matrix with the K data items to produce transformed K data items, the set of P storage elements storing a plurality of intermediate results produced by the sequence of M operations.

Optimization for 3-D graphic transformation using SIMD computations

The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M vertex coordinates corresponding entirely to the N polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.

Processing polygon meshes using mesh pool window

The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.

Efficient utilization of write-combining buffers

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.

Data conversion between floating point packed format and integer scalar format

A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 16-bit number in the integer format. The 16-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

Conversion from packed floating point data to packed 16-bit integer data in different architectural registers

The present invention discloses a method and apparatus for processing strips of data, each strip referencing a plurality of parameter sets stored in a memory. The method comprises: prefetching a plurality of parameter sets referenced in a first strip; performing an operation on each of the prefetched parameter sets; and concatenating a first strip and a second strip to eliminate a memory access latency in the second strip.

Pipelined processing of short data streams using data prefetching

A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.

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Gold River, CA, United States of America

Hsien-Cheng Emile Hsieh