International Business Machines Corporation

Hsieh T Hao

Peter W Markstein

George Radin

John Cocke

Marc Alan Auslander

Miguel M Blaum

Jaishankar Moothedath Menon

Jeffrey N Weiss

Spencer W Ng

Richard L Mattson

Howard E Sachar

Huei Ling

Yannis J Yamour

A data storage system architecture having an array of small data storage disks, organized into logical rows and columns, with each disk coupled to two disk controllers via two independent controller-disk interconnects. No two disks are coupled to the same pair of controllers. In this data storage system architecture, the component disks are arranged in parity groups of variable size. Within each parity group, failure of one disk sector can be recovered through data reconstruction using data from other disks in the parity group. One or more disks can be reserved as hot standbys for substitution on failure, automatically replacing any failing disk.

Two-dimensional disk array

A method and means for encoding data written onto an array of M synchronous DASDs and for rebuilding onto spare DASD array capacity when up to two array DASD fail. Data is mapped into the DASD array using an (M-1)*M data array as the storage model where M is a prime number. Pairs of simple parities are recursively encoded over data in respective diagonal major and intersecting row major order array directions. The encoding traverse covering a topologically cylindrical path. Rebuilding data upon unavailability of no more than two DASDs merely requires accessing the data array and repeating the encoding step where the diagonals are oppositely sloped and writing the rebuilt array back to onto M DASDs inclusive of the spare capacity.

Method and means for encoding and rebuilding data contents of up to two

A method for implementing error-correcting codes for disks, wherein the statistics of error vary according to the radius of the location being accessed. A Reed-Solomon code is selected having data bytes and redundant bytes and an error-correcting capability sufficient to protect against an anticipated worst case or errors. The number of redundant bytes in that code, and thereby the number of correctable errors, is progressively reduced in respective concentric areas of the disk according to the statistics of error for such areas, for thereby progressively reducing the number of correctable errors as the need for error correction capability decreases. For multiband recording, the areas are concentric bands in each of which data is recorded at a clock frequency substantially proportional to its inner diameter; and in such case, the number of redundant bytes is reduced progressively in each successive band toward the innermost band. For conventional recording, the areas are concentric tracks recorded at substantially the same frequency; and in such case, the number of redundant bytes is reduced toward the outermost concentric area. This method may also be used to increase correction capability periodically when capability decreases, due for example to corrosion of a write-once optical disk.

Error correction capability varied with track location on a magnetic or

Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder. The three-input adder of the secondary data flow facility emulates the result of a two-input adder of a primary data flow facility, occuring simultaneously in the two-input primary data flow facility adder, adding the third operand to the emulated result, without delay. The instruction unit decodes the instruction sequence normally to control (k)-at-a-time execution where there are no instruction interlocks or dependencies; to delay execution of dependent instructions until operands become available; and to reinstate (k)-at-a-time execution in a limited number of cases by using the additional capability of the secondary data flow facility to emulate the prerequisite operands. A control unit performs housekeeping to execute the instructions.

(k)-Instructions-at-a-time pipelined processor for parallel execution of

A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

Condition register architecture for a primitive instruction set machine

A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.

Mechanism for implementing one machine cycle executable trap

A mechanism for performing fast and efficient full shift, merge, insert and bit alignment functions within one operating machine cycle of a host primitive instructions set computing system. In general, the circuitry performs a ring shift under control of a mask. The circuitry further combines essentially parallel rotate and mask and merge functions all executable in one machine cycle. The circuitry further allows the provision of powerful bit, digit, and bit rotate with mask instructions which are particularly useful primitive operations for decimal packing and unpacking functions as well as for implementing floating point preshifting and normalization functions.

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Chappaqua, NY, United States of America

Hsieh T Hao