Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsieh-Hung Hsieh

Tzu-Jin Yeh

Chewn-Pu Jou

Fu-Lung Hsueh

Yi-Hsuan Liu

Hong-Lin Chu

Yen-Jen Chen

Chi-Feng Huang

Chia-Chung Chen

Victor Chiang Liang

Fu-Huan Tsai

Han-Min Tsai

Ming Hsien Tsai

Jun-De Jin

Ho-Hsiang Chen

Po-Yi Wu

Huan-Neng Chen

Kuang-Kai Yen

Sa-Lly Liu

Wu-Chen Lin

Ming-Hsien Tsai

Tsung-Hsiung Li

Fan-Ming Kuo

Shen-Iuan Liu

Wei-Li Chen

Tzong-Lin Wu

Yung-Hsu Chuang

Hsiao-Chun Lee

Tsung-Hsiung Lee

Fan-ming Kuo

Chiao-Han Lee

Shih-Hung Lan

Shi-Hung Wang

I-Ting Lee

A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of integrated power-amplifiers coupled to the dividing circuit, each of the plurality of integrated power-amplifiers being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.

Power amplifiers testing system and related testing method

A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

High-implant channel semiconductor device and method for manufacturing the same

An IC includes a device-under-test (DUT) configured to receive a first AC signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal, and first and second detection circuits. Each of the first and second detection circuits includes a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device, a second gain stage in a cascade arrangement with the first gain stage, and a low-pass filter configured to generate a DC signal based on an output signal of the second gain stage.

Test circuit and method

A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.

An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.

A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.

Method of using varainductor having ground and floating planes

A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Buried channel semiconductor device and method for manufacturing the same

A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.

A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.

A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.

Varainductor having ground and floating planes and method of using

A test circuit includes an amplifier configured to receive an AC signal, and output an amplified AC signal based on the AC signal, a first detection circuit configured to generate a first DC voltage having a first value based on an amplitude of the AC signal, and a second detection circuit configured to generate a second DC voltage having a second value based on an amplitude of the amplified AC signal.

A method of detecting a power level of an RF signal includes driving an internal node of a power detection circuit to a DC node voltage level, generating, based on the DC node voltage level, a first component of an output voltage on an output node of the power detection circuit, receiving the RF signal on an input node of the power detection circuit, dividing the RF signal to generate a modulation signal on the internal node, and generating, by at least partially rectifying the modulation signal, a second component of the output voltage on the power detection circuit output node.

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Taipei, Taiwan

Hsieh-Hung Hsieh