National Yang Ming Chiao Tung University

Lite-on Technology Corporation

Macronix International Co., Ltd.

Winbond Electronics Corporation

Lite-on Electronics (guangzhou) Limited

Hsie-Chia Chang

Chen-Yi Lee

Yen-Chin Liao

Chien-Ching Lin

Shih-Jia Zeng

Hsiang-Pang Li

Yi-Min Lin

Shu Lin

Chih-Hao Liu

Chien-Fu Tseng

Jen-Chien Fu

Yu-Ming Huang

Chi-Heng Yang

Yu-Shan Wu

Yar-Sun Hsu

Yen-Yu Chou

Yarsun Hsu

Chih-Wei Liu

Jieh-Tsorng Wu

Ta-Hui Wang

Kelvin Yi-Tse Lai

Chih-Hsiang Hsu

Ming-Wei Lai

Kin-Chu Ho

Yu-Tao Yang

Sung-Shine Lee

Szu-Chi Chung

Chia-Ching Chu

Chen-Yang Lin

Chun-Yuan Yu

Cheng-Chi Wong

Yung-Yu Lee

Jr-Hau Lu

Zih-Cheng He

Yu-Chi Kao

Kuo-Kuang Yen

Jau-Yet Wu

A data transmitting method using an LDPC code as an error correction code is provided. The method includes providing a parity check matrix of LDPC code, wherein the size of the parity check matrix is (m1+m2)&#xd7;(n1+n2); in a sending side, encoding an input data of K bits with a encoder to generate a first block code of (n1+n2) bits, according to the parity check matrix; through a transmitting channel, sending n1 bits of the first block code from the sending side to a receiving side, wherein n2 bits of the first block code are not transmitted; and receiving the n1 bits of the first block code in the receiving side, and using the parity check matrix to perform a decoding algorithm to the received first block code to iterative decodes a second block code of (n1+n2) bits with a decoder. Furthermore, a data decoding method thereof is also provided.

Data decoding method using LDPC code as error correction code and data transmitting method thereof

A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.

Low-density parity-check code scaling method

A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.

Method for generating encoded data that is encoded based on low-density parity-check codes, and method for decoding the encoded data

An encryption/decryption apparatus and a power analysis protecting method thereof are provided. The encryption/decryption apparatus adapted to perform encryption/decryption operation on digital data includes a data encryption/decryption unit, a random number generator, and a power analysis protecting circuit. The data encryption/decryption unit receives the digital data and performs an encryption/decryption operation on the digital data. The random number generator is used to generate random number data, the random number data has N bits, and N is a positive integer. The power analysis protecting circuit generates M kinds of power signals having different levels according to each bit data of the random number data when the random number data is received by the power analysis protecting circuit, and M is equal to the Npower of 2.

Encryption/decryption apparatus and power analysis protecting method thereof

A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N&#x2212;K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q&#x2212;K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q&#x2212;K frozen bits are allocated to the N&#x2212;K frozen bit-channels and the q additional frozen bit-channels.

Extended polar codes

A method and a system for data transmission are provided. The method includes: determining a size of a first block and a first degree distribution for a first data transmission according to a parameter which is related to a hardware specification of a receiving node; determining a channel loss rate of a channel between a sending note and the receiving node when completing the first data transmission; determining a size of a second block and a second degree distribution for a second data transmission according to the channel loss rate; and performing, by the sending node and the receiving node, the second data transmission according to the size of the second block and the second degree distribution.

Method and system for data transmission

A turbo decoder system decodes L-length digital data consisting of a systematic code and 1and 2parity check codes, and includes a trellis controller obtaining the ratio of the bit-number Ep of the 1/2parity check code to the bit-number D of an original systematic code and generating, based on the code rate of the digital data, a trellis control output indicating a target decoding trellis, which is selected by a turbo decoder to perform decoding operations. A zero-patch module patches zeros into the systematic code, and patches, based on the value of Ep/D, one or more zeros into the 1/2parity check code so that parity check bits of the 1/2parity check code and the zero-bit(s) form a periodically depunctured parity check code.

Method and device for de-puncturing turbo-coded digital data, and turbo decoder system

Length-compatible extended polar codes

A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage.

Method and system for determining storing state of flash memory

A readout system includes a sensing module to generate first and second voltage signals with a phase difference associated with an environmental parameter, and a readout module configured to calibrate the phase difference, and to convert the calibrated phase difference into an output code.

Readout system

Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell.

Method and apparatus of measuring error correction data for memory

A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values.

Solid state storage device and sensing voltage setting method thereof

A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.

Fully parallel encoding method and fully parallel decoding method of memory system

A data compensating method for a flash memory is provided. Firstly, a first threshold voltage distribution curve of the cells of the flash memory with a first storing state is acquired. Then, a second threshold voltage distribution curve of the cells of the flash memory with a second storing state is acquired. Then, a first occurrence probability of a first type ICI pattern of the first storing state is calculated according to a statistic voltage range and the first threshold voltage distribution curve. A second occurrence probability of the first type ICI pattern of the second storing state is acquired according to the statistic voltage range and the second threshold voltage distribution curve. During a read cycle, storing states of central cells corresponding to the first type ICI pattern are compensated according to the first occurrence probability and the second occurrence probability.

Data compensating method for flash memory

A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table corresponding to a first neighboring cell. Then, MICI patterns are determined according to N neighboring cells having a significant ICI effect. If the central cell has a first storing state, Mcentral cell threshold voltage shifts corresponding to the MICI patterns are determined according to the voltage shift parameter table, and the first storing state is divided into plural sub-regions. Afterwards, the central cells corresponding to a first number of ICI patterns are classified into a first group of the first storing state. The central cell threshold voltage shifts corresponding to the first number of ICI patterns lie in a first sub-region of the first storing state.

Group classification method for solid state storage device

Growing community of inventors

Hsinchu, Taiwan

Hsie-Chia Chang