Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiao Wen Lee

Shih-Yao Lin

Chih-Han Lin

Ming-Ching Chang

Chen-Ping Chen

Chao-Cheng Chen

Yu-Shan Cheng

Kuei-Yu Kao

Chieh-Ning Feng

Li-Jung Kuo

Chia-Hao Yu

Shu-Yuan Ku

Ya-Yi Tsai

Shu-Uei Jang

Chen-Yui Yang

A semiconductor device includes a plurality of channel layers vertically spaced from one another, a gate structure wrapping around each of the plurality of channel layers; and an inner spacer that is disposed along sidewalls of a lower portion of the gate structure. The inner spacer curves toward the lower portion of the gate structure.

Semiconductor devices and methods of manufacturing thereof

A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.

Semiconductor devices with edge dielectric fin structures and methods of manufacturing thereof

A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.

A semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. The first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.

A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.

A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.

A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.

A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.

A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers.

A method includes forming a dielectric fin over a substrate between a first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins, and the dielectric fin all extend along a first lateral direction. The method includes forming a dummy gate structure that extends along a second lateral direction and includes a first portion and a second portion. The first and second portions overlay the first and second semiconductor fins, respectively, and separate from each other with the dielectric fin. The method includes removing upper sidewall portions of the dielectric fin. The method includes replacing the first and second portions of the dummy gate structure with a first and second active gate structures, respectively.

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Hsinchu, Taiwan

Hsiao Wen Lee