Taiwan Semiconductor Manufacturing Comp. Ltd.

Taipei Medical University

National Health Research Institutes

Hsiao-Wen Chung

Shan-Yu Huang

Huang-Sheng Lin

Meng-Hsiu Hsieh

Ming-Da Cheng

Shih-Chang Chen

Ching-Wen Hsiao

Yi-Lun Chen

Yuan-Yao Chang

Cheng-Yu Chen

Yilun Chen

Yu-Chieh Jill Kao

Duen-Pang Kuo

Chia-Feng Lu

Li-Chun Hung

Wen-Yih Isaac Tseng

Teng-Yi Huang

Hsueh-Heng Lin

Hsu-Hsia Peng

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure with conductive pillar and method for forming the same

A method for fabricating a semiconductor device is provided. The method includes generating a redistribution layer (RDL) layout, wherein the RDL layout comprises a plurality of redistribution lines; determining a first dummy region in the RDL layout according to the redistribution lines; disposing a plurality of first dummy redistribution lines in the first dummy region; performing a first modification process to enlarge at least one of the first dummy redistribution lines; determining the enlarged one of the first dummy redistribution lines as a second dummy region in the RDL layout when an area of the enlarged one of the first dummy redistribution lines is greater than a threshold value; disposing a plurality of second dummy redistribution lines in the second dummy region; and patterning a metal layer according to the RDL layout after disposing the second dummy redistribution lines in the second dummy region.

Semiconductor device and method for fabricating the same

A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Dummy patterns in redundant region of double seal ring

A semiconductor structure includes two circuit regions and two inner seal rings, each of which surrounds one of the circuit regions. Each inner seal ring has a substantially rectangular periphery with four interior corner stress relief (CSR) structures. The semiconductor structure further includes an outer seal ring surrounding the two inner seal rings. The outer seal ring has a substantially rectangular periphery without CSR structures at four interior corners of the outer seal ring. The outer seal ring includes a plurality of first fin structures located between each of the two inner seal rings and a respective short side of the outer seal ring. Each first fin structure is parallel with the respective short side of the outer seal ring. Lengths of the first fin structures gradually decrease along a direction from the inner seal rings to the respective short side of the outer seal ring.

Mandrel fin design for double seal ring

A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.

Semiconductor structure and method for forming features in redundant region of double seal ring

The invention relates to a method for determining ischemic status. The method comprises acquiring magnetic resonance diffusion tensor matrices and obtaining a relative decrease of diffusion magnitude due to the ischemic status from the magnetic resonance diffusion tensor matrices. The invention also relates to a method for assessing stroke onset time. The method comprises acquiring magnetic resonance diffusion tensor matrices and obtaining a relative decrease of pure anisotropy due to stroke from the magnetic resonance diffusion tensor matrices.

Method for determining ischemic status or assessing stroke onset time of a brain region

A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure and method for forming the same

In one aspect, in general, a method is provided for detecting temperature and protein denaturation of a tissue during thermal therapy. The method includes generating a plurality of MR pulse sequences that include a first group of pulse sequences and a second group of pulse sequences, and receiving a plurality of response signals that include a first and second group of response signals in response to the first and second groups of pulse sequences, respectively. A first information associated with a degree of protein denaturation of the tissue is determined based on the first and second groups of response signals. A second information associated with a temperature of the tissue is determined based on at least some of the plurality of response signals.

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Taipei, Taiwan

Hsiao-Wen Chung