Taiwan Semiconductor Manufacturing Comp. Ltd.

Synopsys, Inc.

Synopsys Taiwan Co., Ltd.

Hsiao-Tzu Lu

Kuei Shun Chen

Chin-Hsiang Lin

Tsiao-Chen Wu

George Liu

Vencent Chang

Hua-Shu Ivan Wu

Chia-Hsiang Lin

Duncan Robert McDonald

Chih-Wei Yuan

Wen-Lung Kang

Shau-Lin Shue

Ching-Hua Hsieh

Tsai-Sheng Gau

Huan-Just Lin

Yung-Sung Yen

Kuei-Shun Chen

Chia-Chu Liu

Hui-Chi Huang

Mu-Chi Chiang

Fu-Jye Liang

Burn-Jeng Lin

Hung Chang Hsieh

Yu-Chi Su

Hsueh-Hung Fu

Bi-Fen Wu

Yuh-Sen Chang

Yao-Kwang Wu

Chun-Kung Chen

Chia-Sui Hsu

Ming-I Lai

Keui Shun Chen

Tsai-Cheng Gau

A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.

Manipulating parameterized cell devices in a custom layout design

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

Field effect transistors and method of forming the same

A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively.

Method of schematic driven layout creation

The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.

Method for patterning a photosensitive layer

Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.

Methods and systems for lithography alignment

Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.

System for overlay measurement in semiconductor manufacturing

A method for photolithography in semiconductor manufacturing includes providing a substrate for a wafer and providing a mask for exposing the wafer. The wafer is exposed by utilizing a combination of high angle illumination and focus drift exposure methods.

System and method for photolithography in semiconductor manufacturing

A method for photolithography in semiconductor manufacturing includes providing a mask with first and second focus planes for a wafer. The wafer includes corresponding first and second wafer regions. The first wafer region receives a first image during a first exposure utilizing the first focus plane. The second wafer region receives a second image during a second exposure utilizing the second focus plane.

A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the pattern can be identified based on the reflective beams.

Method of overlay measurement for alignment of patterns in semiconductor manufacturing

A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another embodiment, a first layer is formed over a first side of a substrate and over a second side of the substrate. A second layer is formed over the first layers and the wafer is then flash annealed.

Method of heating semiconductor wafer to improve wafer flatness

Growing community of inventors

Hsinchu, Taiwan

Hsiao-Tzu Lu