Amdahl Corporation

Hsiao-Peng S Lee

Stephen J Rawlinson

Stephen S Si

Gene M Amdahl

John C Oneto

David Jarosh

Stephen F Stuart

Ulrich Spannagel

The times-two (.times.2) through times-nine (.times.9) multiples of a supplied multi-digit BCD number are produced using one machine cycle for performing a set-up operation and thereafter one additional machine cycle for producing all the .times.2-.times.9 multiples. A multiples generating circuit in accordance with the invention comprises: (a) an operand-storing register (OSR); (b) a multiple-storing register (MSR); (c) a multiplexer having a first input coupled to the output of the operand-storing register (OSR) and a second input coupled to the output of the multiple-storing register (MSR); (d) a .times.3 unit having an input coupled to the output of the multiplexer and an output coupled to the input of the MSR; (e) a first .times.2 unit having an input coupled to the output of the OSR; (f) a second .times.2 unit having an input coupled to the output of the first .times.2 unit; (g) a third .times.2 unit having an input coupled to the output of the second .times.2 unit; (h) a fourth .times.2 unit having an input coupled to the output of the MSR; (i) a .times.5 unit having an input coupled to the output of the OSR; and (j) a .times.7 unit having an input coupled to the output of the OSR.

Method and apparatus for generating multiples of BCD number

An instruction execution unit receives instructions and, in turn, provides a sequence of control words to specify the sequential processing of the operand data provided with the instruction. A sequencer nominally issues a first sequence of control words corresponding to the instruction. The sequencer includes a sequence selector for selecting a second sequence of control words for issuance by the sequencer. Control logic is provided to determine from the operand data, concurrent with the issuance of at least the first issued control word, whether the operand data is ideal with respect to the instruction, where ideal is defined as the predicted nonoccurence of underflow and overflow conditions. On determining that the operand data is ideal with respect to the instruction, the sequence selector is caused to select the second sequence of control words for issuance.

Pipelined data processing system utilizing ideal floating point

Disclosed is a signed multiplier for use in a data processing system that handles 2's complement operands. The signed multiplier operates to form a preliminary product independently of the signs of the multiplier and multiplicand. While the multiplication is in progress, the signs of the multiplier and multiplicand are checked. For multiplications where either one of the operands (multiplier or multiplicand) is negative, the preliminary product is modified by one or two correction factors. The correction factors are multiplies of the 2's complements of the operands. The correction factor or factors are added to the preliminary product to form the final product.

Signed multiplier with three port adder and automatic adjustment for

An ancillary execution unit is interfaced to a primary execution unit of a data processing system where the ancillary unit operates faster than the primary for certain instructions and allows for bypassing the slower unit. The primary execution unit has an instruction input receiving an instruction, an operand input receiving data and an operand output transferring data from the primary execution unit to the data processing system. The ancillary execution unit obtains the instruction from the instruction input, obtains the data from the operand input, performs the function indicated by the instruction to the data, and returns data to the primary execution unit.

Ancillary execution unit for a pipelined data processing system

Disclosed is a control unit including a flexible decoder unit providing control patterns for controlling functional units in data processing equipment. The control unit includes hardwired decoder logic which decodes a multi-bit key to provide primary decoded outputs as control patterns. The decoder unit also decodes one or more alternate decoded outputs for future use. The decoder includes a plurality of flexibility inputs which, when connected to an alternate decoded output, provide new control patterns and thus provides flexibility to the hardwired decoder. Because of the flexibility, the control patterns formed by the hardwired decoder can be readily changed. The flexible hardwired decoder is of great value, therefore, when design changes are desired in a computer.

Flexible computer control unit

A two control store scheme with instruction execution overlay is shown in a data processing system execution unit having a two-state pipeline. The first control store controls the first-stage facilities during the first cycle of instruction execution and points to the initial location of the second control store. The second control store controls the second-state facilities during the final cycle of instruction execution. The second control store also controls the facilities of both stages during the intermeidate cycles of instruction requiring more than two cycles to execute. Because the second control store controls only the second-stage facilities during the final cycle, execution of the first cycle of the following instruction can take place concurrently within the first-stage facilities under the control of the first control store.

Two-stage pipelined execution unit and control stores

A sequencing apparatus and method employing two or more control stores for use within a data processing system. Where two-way branching exists, first and second control stores each provide control words for the common control of units within a data processing system. Whenever a branch is specified, a corresponding branch address is provided in the first control store for addressing the second control store. A nonbranch address is provided for addressing the first control store. The nonbranch address and the branch address each are employed to access concurrently control words from the first and second control stores. Upon the determination of the state of the branch condition, the appropriate one of the previously accessed control words is selected without delay and without need for an additional cycle to access the control stores.

Multiple module control store for use in a data processing system

Disclosed is a method and apparatus for predicting the condition code of a condition-code-setting instruction by comparing operands in a data processing system. An operand comparator includes one or more half-adders to predict carry outs at an early time. The comparator is used in a data processing system which is operative in response to instructions having operation codes for specifying operations to be executed. The instructions also have operand fields for identifying operands to be utilized in connection with executing the instructions.

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Sunnyvale, CA, United States of America

Hsiao-Peng S Lee