United Microelectronics Corp.

Other

Hsiao-Ling Lu

Teng-Chun Tsai

Tri-Rung Yew

Wen-Yi Hsieh

Art Yu

Neng-Kuo Chen

Kuo-Tai Huang

Chia-Jung Hsu

Gwo-Shii Yang

Michael W C Huang

Chih-An Huang

Michael W Huang

Hsiu-Chuan Chu

Li-Yeat Chen

Chia-Rung Hsu

Michael Wc Huang

A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.

Chemical mechanical polishing process for forming shallow trench isolation structure

A method of fabricating a shallow trench isolation structure is disclosed. On a substrate, a pad oxide layer and a mask layer are successively formed. The pad oxide layer, the mask layer and a portion of the substrate are patterned to form a trench. After performing a rapid wet thermal process, a liner layer is formed on the exposed surface of the substrate, including the exposed silicon surface of the substrate in the trench and sidewalls and the surface of the mask layer. An oxide layer is deposited over the trench and the substrate and fills the trench. A planarization process is performed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to complete the shallow trench isolation structure.

Method for forming shallow trench isolation structure

This invention provides a method of forming a self-aligned silicide of a semiconductor wafer, the surface of the semiconductor wafer comprising at least one silicon device. A cobalt-containing metallic layer is formed on the semiconductor wafer which covers on the surface of the silicon device. A first thermal treatment process is performed to rapidly heat the semiconductor wafer up to 300&tilde;500&deg; C. for 10&tilde;50 seconds and form Co,Si on the surface of the silicon device. A second thermal treatment process is performed to rapidly heat the semiconductor wafer up to 400&tilde;680&deg; C. for 20&tilde;50 seconds and then cool down the semiconductor wafer afterwards so as to convert Co,Si into CoSi. An etching process is performed to remove the metallic layer. A third thermal treatment process is performed to rapidly heat the semiconductor wafer up to 700&tilde;950&deg; C. for 30&tilde;60 seconds and then cool down the semiconductor wafer afterward so as to convert CoSi into the self-aligned silicide.

Method of forming a self-aligned silicide on a semiconductor wafer

A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.

Method for testing leakage current caused self-aligned silicide

A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.

Method of fabricating shallow trench isolation

A method for fabricating a semiconductor device. A substrate having a gate is provided. An ion implantation process is performed to form lightly doped source/drain region in the substrate. A liner layer and an insulation layer are formed over a substrate in sequence. A portion of the insulation layer is removed by an anisotropic etching process. The insulation layer remaining on sidewalls of the gate is used as a spacer. A top of the spacer is substantially level with an upper surface of the liner layer. An ion implantation process is performed to form heavily doped source/drain region in the substrate. A portion of the spacer is removed by wet etching. As a result, a top surface of the spacer is lower than the upper surface of the gate. The method can increase the exposed surface of the gate and maintain sufficient width of the lightly doped source/drain region to prevent the hot carrier effect and the short channel effect.

Method for fabricating semiconductor device

Growing community of inventors

Jhudong, Taiwan

Hsiao-Ling Lu