Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiao-Hui Chen

Cheok-Kei Lei

Clement Hsingjen Wann

Chih-Sheng Chang

Yi-Tang Lin

Chien-Wen Chen

Shu-Yu Chen

Yu-Ning Chang

Mu-Jen Huang

Yu-Sian Jiang

Po-Tsun Chen

Yue-Der Chih

Cheng-Hsiung Kuo

Shiue Tsong Shen

Shu-Chen Chang

The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

Performance-driven and gradient-aware dummy insertion for gradient-sensitive array

A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.

System and methods for converting planar design to FinFET design

A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint.

Automatic flow of megacell generation

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities

A method for revising a patterned conductor layer and a system for revising the patterned conductor layer employ an unoccupied equivalent wiring location. The unoccupied equivalent wiring location is provided in each of a series of wiring layout records. At least one optional wiring pattern may be formed in the unoccupied equivalent wiring location. The method and system provide for extending to all of the series of wiring layout records an optional wiring pattern and an interconnect option formed within a single one of the series of wiring layout records.

Growing community of inventors

Hsinchu, Taiwan

Hsiao-Hui Chen