Advanced Semiconductor Engineering, Inc.

Hsiao-Chuan Chang

Tsung-Yueh Tsai

Yi-Shao Lai

Ming-Hsiang Cheng

Ming-Kun Chen

Chang-Lin Yeh

Ping-Cheng Hu

Pao-Huei Chang Chien

Chien-Wen Chen

Jiunn Chen

Hsu-Yang Lee

Tsan-Hsien Chen

A light emitting package includes a metal plate, a plurality of LED chips, a plurality of leads and a molding compound. The metal plate has a first surface and a second surface, and is bent into two chip mounting portions, wherein an inclination angle is between the chip mounting portions. The LED chips are mounted on the first surface and the second surface of the chip mounting portions. The leads are disposed adjacent to the metal plate and electrically connected to the LED chips. The molding compound encapsulates the LED chips and a part of the lead.

Light emitting package and LED bulb

A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.

Semiconductor package

The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.

A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.

Semiconductor device package having a buffer structure and method of fabricating the same

A first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.

Semiconductor device package

A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.

Semiconductor device package having a jumper chip and method of fabricating the same

A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof

The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased.

Semiconductor package and method for making the same

A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.

Bonding strength measuring device

A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.

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Kaohsiung, Taiwan

Hsiao-Chuan Chang