Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Hon Hai Precision Industry Co., Ltd.

Hsiang-Wei Liu

Tai-I Yang

Chia-Tien Wu

Wei-Chen Chu

Tien-Lu Lin

Shau-Lin Shue

Yu-Chieh Liao

Yung-Chih Wang

Hsiang-Lun Kao

Jian-Hua Chen

Cheng-Chi Chuang

Hai-Ching Chen

Hsin-Yen Huang

Shao-Kuan Lee

Cheng-Chin Lee

Yung-Hsu Wu

Ting-Hao Wang

Li-Lin Su

Hsiang-Huan Lee

Yao-Jen Yang

Meng-Sheng Chang

Jen-Wei Tsai

Wen-Hsien Chuang

Andy Yang

An integrated circuit (IC) device includes a transistor and a metal fuse structure including a metal fuse electrically connected to the transistor, and a first metal line in parallel with the metal fuse and adjacent to a first portion of the metal fuse in a first direction. The first portion has a first width, and the metal fuse includes a second portion having a second width larger than the first width, and a first contour between the first and second portions and aligned with a first end of the first metal line.

Multiple pattern metal fuse device, layout, and method

An integrated circuit (IC) device includes transistor and programmable structure regions. The transistor region includes a source structure configured to receive a reference voltage, a first portion of a drain structure, and a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal. The programmable structure region includes a second portion of the drain structure, a first signal line configured to receive an operational voltage, a second signal line, a gate via underlying and electrically connected to the first signal line, and a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line. Portions of the first signal line including a gate via location and the second signal line including a drain via location are positioned in parallel in a same metal layer of the IC device.

Memory device, layout, and method

In one aspect of the present disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes a first conductive structure extending in a first direction, the first conductive structure coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced from the first conductive structure in a second direction perpendicular to the first direction; a dielectric material extending in the second direction and disposed over, in a third direction perpendicular to the first direction and the second direction, the first conductive structure; and a via structure disposed over the second conductive structure and in contact with the dielectric material, wherein the dielectric material is configured to create a channel between the first conductive structure and the via structure when a voltage is applied to the second conductive structure.

Metal fuse structure by via landing

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Method of providing a workpiece including low resistance interconnect low-resistance interconnect

A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.

Semiconductor device and method of operating the same

A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Metal line structure and method

The present disclosure provides an interconnect structure, including a first metal line, a second metal line spaced away from the first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, wherein a shortest distance between the second portion and the second metal line is in a range from 50 Angstrom to 200 Angstrom, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, the entire first portion and the entire second portion are under a coverage of a vertical projection area of the third portion, a first layer, and a second layer over the first layer.

Interconnect structure and manufacturing method for the same

Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Multi-metal fill with self-aligned patterning and dielectric with voids

Semiconductor structure including low-resistance interconnect and integrated circuit device having the same

A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and an analog-to-digital converter. The sensor generates a first sensing result corresponding to an ambient temperature based on a first condition and generates a second sensing result corresponding to the ambient temperature based on a second condition. The second sensing result is different from the first sensing result. The analog-to-digital divides the first sensing result and the second sensing result to obtain a quotient value and generates an output digital code value corresponding to the ambient temperature according to the quotient value.

Temperature sensing device and temperature sensing method

A method for forming an interconnect structure is provided. The method for an interconnect structure includes forming a first metal material over a semiconductor substrate, and forming a first mask element over the first metal material. The first mask element has an opening through the first mask element. The method for forming the interconnect structure also includes forming a second metal material over the first mask element and the first metal material and in the opening, and forming a second mask element corresponding to the opening and over the second metal material. The method for forming the interconnect structure also includes etching the second metal material and the first metal material using the second mask element and the first mask element to form a via and a first metal line respectively.

Interconnect structure and method for forming the same

The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

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Tainan, Taiwan

Hsiang-Wei Liu