Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiang-Wei Lin

Chung-Chi Ko

Wan-Yi Kao

Wei-Ken Lin

Li Chun Te

Shu Ling Liao

Guan-Yao Tu

Te-En Cheng

Yi-Nien Su

Yu-Ting Huang

Chia-Ho Chen

Bo-Hung Lin

Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Low-K feature formation processes and structures formed thereby

A semiconductor structure includes a gate structure over a substrate. The structure also includes a source/drain epitaxial structure formed on opposite sides of the gate structure. The structure also includes a contact structure formed over the gate structure. The structure also includes a metal layer formed over the contact structure. The structure also includes a cap layer formed over the metal layer. The structure also includes a first etch stop layer including a metal compound formed over the cap layer. The structure also includes a second etch stop layer including nitrogen formed over the first etch stop layer. The structure also includes a via structure that passes through the first etch stop layer and the second etch stop layer. The bottom surface of the cap layer is level with the bottom surface of the first etch stop layer.

Semiconductor structure and method for forming the same

A device includes a first conductive feature in an insulating layer; a dielectric layer over the first conductive feature; a second conductive feature in the dielectric layer, wherein the second conductive feature is over and physically contacting the first conductive feature; an air spacer encircling the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; a metal cap covering the second conductive feature and extending over the air spacer, wherein the air spacer is sealed by a bottom surface of the metal cap; a first etch stop layer on the dielectric layer, wherein a sidewall of the first etch stop layer physically contacts a sidewall of the metal cap; and a second etch stop layer extending on a top surface of the metal cap and a top surface of the first etch stop layer.

Conductive features with air spacer and method of forming same

Low-k feature formation processes and structures formed thereby

A method includes forming a first conductive line and a second conductive line in a dielectric layer, etching a portion of the dielectric layer to form a trench between the first conductive line and the second conductive line, and forming a first etch stop layer. The first etch stop layer extends into the trench. A second etch stop layer is formed over the first etch stop layer. The second etch stop layer extends into the trench, and the second etch stop layer is more conformal than the first etch stop layer. A dielectric material is filled into the trench and over the second etch stop layer. An air gap is formed in the dielectric material.

Multi-barrier deposition for air gap formation

The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench.

Semiconductor structure and method of making the same

A semiconductor structure includes a first low-k dielectric layer disposed over a semiconductor substrate, a first conductive feature and a second conductive feature disposed in the first low-k dielectric layer, a second low-k dielectric layer disposed in the first low-k dielectric layer and interposed between the first conductive feature and the second conductive feature, where the second low-k dielectric layer includes an air gap, and an etch-stop layer disposed at an interface between the first low-k dielectric layer and the second low-k dielectric layer. The first low-k dielectric layer includes carbon whose concentration is graded in a direction away from the etch-stop layer.

Structure for interconnection

A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.

FinFET device and method of manufacture

A semiconductor structure includes a semiconductor substrate and a conductive feature formed over the semiconductor substrate, an etch stop layer formed over the conductive feature, a dielectric layer formed over the etch stop layer, and a contact formed in a contact trench within the dielectric layer. The bottom of the contact is disposed over a top surface of the conductive feature. The semiconductor structure further includes a self-aligned sealing oxide layer formed on the dielectric layer. The self-aligned sealing oxide layer directly contacts the dielectric layer from a bottom-most portion of the self-aligned sealing oxide layer to a top-most portion of the self-aligned sealing oxide layer.

Semiconductor structure and method making the same

A semiconductor structure includes a first dielectric layer disposed over a substrate; a first metal feature and a second metal feature embedded in the first dielectric layer and spaced from each other; an etch stop layer disposed between the first and second metal features and on sidewalls of the first dielectric layer; a second dielectric layer disposed over the etch stop layer and between the first and second metal features; and an air gap surrounded by the second dielectric layer and disposed between the first and second metal features.

Interconnection structure having air gap

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a fin structure over a substrate. The semiconductor device structure also includes a gate structure over the fin structure. The semiconductor device structure further includes a source/drain structure adjacent to the gate structure. In addition, the semiconductor device structure includes a first spacer layer between the gate structure and the source/drain structure, wherein the first spacer layer has a protruding portion extending towards the substrate.

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Hsiang-Wei Lin