Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiang-tai Lu

Chih-Hsuan Tai

Ming-Chung Wu

Kuo Wen Chen

Shin-Puu Jeng

Shuo-Mao Chen

Feng-Cheng Hsu

Mill-Jer Wang

Chih-Hsien Lin

Chen-Hua Lin

Chao-Hsiang Yang

Cheng-Yi Hong

Kuo-Wen Chen

Dai-Jang Chen

Yu-wei Chiu

A method of manufacturing a semiconductor structure, comprising: disposing a dielectric layer over a semiconductive wafer defined with a plurality of active regions and a scribe line region surrounding each of the plurality of active regions; forming a plurality of interconnect structures within the dielectric layer, wherein the formation of the plurality of interconnect structures includes forming a plurality of first testing pads within the scribe line region and at least partially exposed through the dielectric layer; and sawing the semiconductive wafer along the scribe line region to form a first interposer and a second interposer, wherein each of the plurality of first testing pads is at least partially removed by the sawing of the semiconductive wafer.

Semiconductor structure with testing pads and method of manufacturing thereof

A semiconductor structure includes a substrate, a capacitor disposed in the substrate, an interconnect structure disposed over the substrate, and a first doped region disposed in the substrate. The interconnect structure includes a first via structure coupled to the substrate, and a second via structure coupled to the capacitor. The first doped region is disposed under the first via structure. The first doped region includes p-type or n-type dopants.

Semiconductor package structure and method for forming the same

A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Semiconductor structure and manufacturing method thereof

Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

Delamination sensor

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HSINCHU COUNTY, Taiwan

Hsiang-tai Lu