Taiwan Semiconductor Manufacturing Comp. Ltd.

Pixart Imaging Incorporated

Hsiang Sheng Liu

Chin-Szu Lee

Cheng-Yi Wu

Yu-Hung Cheng

Chia-Chun Hung

Ren-Hua Guo

Li-Hsuan Chu

Chen Liang Chang

Wen-Chin Chen

Chih Yen Wu

Ching-Wen Wen

Chien Jung Huang

Ming Tsan Kao

Liang Szuma

Chien-Ming Chung

Ding-Shan Wang

Chia Cheun Liang

Yu Han Chen

Chih Chung Tsai

Ching Chih Chen

Yen Min Chang

Shih Chang Chi

Kuo Jui Sun

Jing-Chuan Hsieh

A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.

Dielectric film for semiconductor fabrication

A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

Semiconductor epitaxy bordering isolation structure

There is provided a human interface device including a control chip and a plurality of control components. The control chip includes a voltage detection circuit coupled to the plurality of control components via a multiplexing pin and detects a voltage value on the multiplexing pin through the voltage detection circuit thereby identifying an operating state of the plurality of control components.

Human interface device

There is provided a mouse device including a control chip and at least one control component. The control chip includes a voltage detection circuit coupled to the at least one control component through at least one multiplexing pin and detects at least one voltage value on the at least one multiplexing pin using the voltage detection circuit thereby identifying an operating state of the at least one control component.

Mouse device

A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator.

Frequency calibration device and method for programmable oscillator

A programmable memory device includes a plurality of one-time programmable (OTP) memory units, a search unit, a writing unit, and a reading unit. Each OTP memory unit is assigned an address. The search unit searches for the first writable OTP memory unit from the plurality of OTP memory units in a writing operation, or searches for the last programmed OTP memory unit from the plurality of OTP memory units in a reading operation. The writing unit writes data to be written and the bit length of the data to the first writable OTP memory unit. The reading unit sequentially reads data from the last programmed OTP memory unit.

Programmable memory device and memory access method

A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than or equal to a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator.

A method is disclosed for sealing the edge of a wafer against slurry debris and contaminants that are encountered during grinding and backlapping of a semiconductor substrate. This is accomplished by depositing a photosensitive polyimide as a dielectric material on a wafer and mounting the wafer on a chuck. A light source is introduced above the wafer and close to the edge of the wafer. The chuck is then spun by means of a spindle, thus exposing an outer ring of the circumferential edge of the wafer to light source. Because polyimide behaves like a negative resist in the art of lithography, the exposed ring is fixed in place such that when the wafer is next developed, only the unexposed polyimide corresponding to the scribe line patterns is dissolved forming &ldquo;scribe channels&rdquo;, while leaving the ring in tact all along the circumference of the wafer. This wafer edge exposure (WEE) then forms an edge, which, in conjunction with a grinding tape, seals the perimeter of the wafer, thus preventing the polishing contaminants from entering the scribe channels.

Use of wee (water edge exposure) to prevent polyimide

A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.

Growing community of inventors

Hsin-Chu, Taiwan

Hsiang Sheng Liu