Macronix International Co., Ltd.

Hsiang-Pang Li

Tei-Wei Kuo

Yuan-Hao Chang

Yu-Ming Chang

Hung-Sheng Chang

Yung-Chun Li

Cheng-Yuan Wang

Yu-Ming Huang

Chao-I Wu

Tzu-Hsiang Su

Chia-Lin Yang

Kin-Chu Ho

Win-San Khwa

Hsie-Chia Chang

Pi-Cheng Hsiu

Nai-Ping Kuo

Wei-Chieh Huang

Chih-Chang Hsieh

Ting-Yu Liu

Hsi-Chia Chang

Li-Chun Huang

Chien-Hsin Liu

Ping-Hsien Lin

Chih-Huai Shih

Hsing-Chen Lu

Shu-Yin Ho

Chun-Feng Wu

Yao-Wen Kang

Hsiang-Yun Cheng

Chun-Hsiung Hung

Hang-Ting Lue

Chung-Kuang Chen

Hsin-Yi Ho

Kuo-Pin Chang

Wei-Chen Wang

Han-Wen Hu

Yi-Te Shih

Ming-Liang Wei

Chien-Chung Ho

Bo-Rong Lin

Ti-Wen Chen

Ren-Shuo Liu

Win San Khwa

Cheng-Hsuan Li

Ye-Jyun Lin

Shu-Hsien Liao

Shih-Fu Huang

Sheng-Chang Kuo

Che-Wei Tsao

Po-Chao Fang

Kun-Cheng Hsu

Hsin-Yu Chang

Shang-Xuan Zou

Chun-Ta Lin

Ping-Chun Chang

Meng-Yen Chuang

Chi-Hao Chen

Chung-Jae Doong

Tzu-Hsien Yang

I-Ching Tseng

Nai-Jia Dong

A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Memory system for maintaining data consistency and operation method thereof

A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Neural network computation method using adaptive data representation

A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.

Computation method and apparatus exploiting weight sparsity

A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Neural network computation method and apparatus using adaptive data representation

The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.

Memory system, method of operating memory, and non-transitory computer readable storage medium

An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

Encoder, decoder, encoding method and decoding method based on low-density parity-check code

Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

Management system for managing memory device and management method for managing the same

A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.

Polar code generating method, and electronic device and non-transitory computer-readable storage medium therefor

A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N&#x2212;K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q&#x2212;K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q&#x2212;K frozen bits are allocated to the N&#x2212;K frozen bit-channels and the q additional frozen bit-channels.

Extended polar codes

A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

Data allocating method and electric system using the same

A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a code word through a polar code transformation. Select a boundary bit-channel among the bit-channels according to a first ranking list for the bit-channels. Identify a target memory cell among the memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation. Decrease a raw bit error rate of the target memory cell.

Control method for memory device and memory controller

A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.

Method, apparatus, and storage medium for writing data into persistent storage device

A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

Memory device and operating method of same

A cache system is provided. The cache system includes a first cache and a second cache. The first cache is configured for storing a first status of a plurality of data. The second cache is configured for storing a table. The table includes the plurality of data arranged from a highest level to a lowest level. The cache system is configured to update the first status of the plurality of data in the first cache. The cache system is further configured to update the table in the second cache according to the first status of the plurality of data.

Cache controlling method for memory system and cache system thereof

An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.

Erasing method and memory device using the same

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Zhubei, Taiwan

Hsiang-Pang Li