Industrial Technology Research Institute

Elite Semiconductor Memory Technology, Inc

Etron Technology, Inc.

Hsiang-Ming J Chou

Chien-Shao Tang

Chih-Yuan Lu

Hsiao-Chin Tuan

Hu H Chao

Kuo-Liang Pan

Ting-Jui Lin

Chien-Feng Tseng

Yi-Chiu Tsai

Fang-Yu Chang

Hsin-Han Chen

An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.

Electrostatic discharge protection device and layout design thereof

There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.

Configurable electrostatic discharging power clamp and related integrated circuit

A method for the fabrication of high density dynamic random access memory (DRAM) devices with particular emphasis on the capacitor formation. The capacitor is formed using layers of doped and undoped polysilicon. The layers are patterned anisotropically so as to have their remaining portions over the planned capacitor areas, wherein a portion of the layers remains over both the gate structure and the field oxide areas. Then selective etching of the portion of doped polysilicon layer is accomplished using phosphoric acid at a temperature of more than abut 140.degree. C. to create an undercut of the undoped polysilicon layer. The capacitor is completed using a dielectric layer and a top electrode layer.

Process of fabricating a high capacitance storage node

The method of forming an integrated circuit field effect transistor having a gate electrode, source and drain elements with buried contacts to a silicon substrate. A gate silicon oxide layer is formed on the silicon substrate. An in-situ doped layer of polysilicon is formed over the gate silicon oxide layer. An opening is formed in the doped polysilicon layer and the silicon oxide layer to the silicon substrate at the location of the buried contacts. A layer of undoped polysilicon is deposited over the doped polysilicon layer and in the opening to the silicon substrate. Doping by ion implantation of the undoped polysilicon layer is done to form a doped polysilicon gate electrode/buried contact layer. The polysilicon gate electrode/buried contact layer is patterning and etching to form the gate electrode of said transistor and buried contact layer. The source and drain regions are implanted using said polysilicon gate electrode pattern as a mask. The structure is heated to form the buried contact to at least one of the source and drain regions. Alternatively, a contact to an existing device region within the substrate may be contacted using a similar multiple layer polysilicon method.

Fabrication of transistor contacts

A new method to produce a microminiturized capacitor having a roughened surface electrode is achieved. The method involves depositing a first polycrystalline or amorphous silicon layer over a suitable insulating base. The silicon layer is either in situ heavily, uniformly doped or deposited undoped and thereafter heavily doped by ion implantation followed by heating. The structure is annealed at above about 875.degree. C. to render any amorphous silicon polycrystalline and to adjust the crystal grain size of the layer. The polysilicon surface is no subjected to a solution of phosphoric acid at a temperature of above about 140.degree. C. to partially etch the surface and cause the uniformly roughened surface. A capacitor dielectric layer is deposited thereover. The capacitor structure is completed by depositing a second thin polycrystalline silicon layer over the capacitor dielectric layer.

Method for producing a roughened surface capacitor

A method for forming a multilayer contact to a device region through an insulating layered structure is described. An opening is formed through the insulating layered structure to the device region. A barrier metal layer is deposited over the device region and the insulating layered structure both above and on the sides of the opening. An in situ doped polysilicon layer is deposited over the barrier metal layer. A thin layer of metal is deposited over the polysilicon layer. The remaining portion of the opening is filled and the thin layer of metal is covered with undoped polysilicon. The undoped polysilicon is etched until the thin metal film is reached to thereby leave the opening filled. An aluminium metallurgical layer is deposited thereover to complete the multilayer contact.

Growing community of inventors

Hsinchu, Taiwan

Hsiang-Ming J Chou