Macronix International Co., Ltd.

International Business Machines Corporation

Qimonda Ag

Qimonda North America Corporation

Macronix Internationalco., Ltd.

Marconix International Co., Ltd.

Hsiang-Lan Lung

Erh-Kun Lai

Chung H Lam

Matthew Joseph Breitwisch

Yi-Chou Chen

Yen-Hao Shih

Huai-Yu Cheng

Thomas Happ

Bipin Rajendran

Ming-Hsiu Lee

Shih-Hung Chen

Eric Andrew Joseph

Chieh-Fang Chen

Chao-I Wu

Alejandro Gabriel Schrott

Min Yang

I-Ting Kuo

Shue-Shuen Chen

Simone Raoux

Wei-Chih Chien

Jan Boris Philipp

Hsin-Yi Ho

Tung-Cheng Kuo

Hang-Ting Lue

ChiaHua Ho

Matthew Joseph BrightSky

Tien-Yen Wang

Ruichen Liu

Rui-Chen Liu

Roger W Cheek

Ming Hsiu Lee

Rich Liu

Michael F Lofaro

Christopher P Miller

Geoffrey W Burr

Tzu-Hsuan Hsu

Nanbo Gong

Shih-Ping Hong

Wanki Kim

Sheng-Chih Lai

Ming-Hsiang Hsueh

Shih Hung Chen

Chiao-Wen Yeh

Shih-Chin Lee

Chieh Fang Chen

Hsin Yi Ho

Chia Hua Ho

Tu-Shun Chen

Cheng-Wei Cheng

Yu Zhu

Stephen Mark Rossnagel

Thomas Nirschl

Edward William Kiewra

Chih-Yuan Lu

Kuang-Yeu Hsieh

Mark C Lamorey

Chun Hsiung Hung

Scott C Lewis

Chia-Hua Ho

Chia-Jung Chen

Philip L Flaitz

Tai-Bor Wu

Frieder Heinrich Baumann

Richard C Jordan

Che-Min Lin

Sheng Chih Lai

Yung-Han Ho

Li-Hsin Chuang

Ching Wei Tsai

Hsueh Yi Lee

Chung-Hon Lam

Yenhao Shih

Jiun-Yi Tseng

A high bandwidth non-volatile memory (NVM) is described suitable for providing neural network weight data to an AI accelerator processing core or cores. An artificial intelligence (AI) inference memory device employing the high bandwidth NVM technology as described herein can comprise a logic layer die including channel logic implementing connections between a plurality of channels for conducting data to and from an accelerator core via a bus and a plurality of non-volatile memory (NVM) dies stacked vertically one above another, forming a layered vertical stack of NVM dies, each of the NVM dies including at least one memory chip and a plurality of direct vertical connections to a corresponding channel in the logic layer.

High bandwidth non-volatile memory for AI inference system

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

Reconfigurable AI system

Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

3D virtual ground memory and manufacturing methods for same

A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.

Semiconductor structure and endurance test method using the same

A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

3D memory with confined cell

A method comprises a first block of memory cells to store an input array, and a second block of memory cells. Pooling circuitry is operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values. Writing circuitry is operatively coupled to the second block to store the array of output values in the second block of memory cells. Analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function. The writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.

In-memory data pooling for machine learning

A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array

A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

Semiconductor structure and a method for manufacturing the same

A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Memory unit, array and operation method thereof

A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.

Array of pillars located in a uniform pattern

A phase-change material having specific SiOdoping into special Ge-rich GeSbTematerial is described. Integrated circuits using this phase-change material as memory elements in a memory array can pass the solder bonding criteria mentioned above, while exhibiting good set speeds and demonstrating good 10 year data retention characteristics. A memory cell described herein comprises a first electrode and a second electrode; and a memory element in electrical series between the first and second electrode. The memory element comprises a GeSbTephase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %.

High thermal stability SiOdoped GeSbTe materials suitable for embedded PCM application

A memory material and a memory device applying the same are provided. The memory material is a chalcogenide doped with carbon atom. The chalcogenide contains arsenic (As) atom, selenium (Se) atom, germanium (Ge) atom and silicon (Si) atom.

Memory material, and memory device applying the same

A memory device includes a stack structure, a memory element, a channel element, and a semiconductor layer. The stack structure includes a source layer, an insulating layer and gate electrode layers. The insulating layer is on the source layer. The gate electrode layers are on the insulating layer. The memory element is on electrode sidewall surfaces of the gate electrode layers. Memory cells are defined in the memory element between the channel element and the gate electrode layers. The semiconductor layer is electrically connected between the source layer and the channel element. The semiconductor layer and the source layer have an interface therebetween. The interface is at a location on an inside of an insulating sidewall surface of the insulating layer with a lateral offset relative to the insulating sidewall surface.

Memory device with lateral offset

A three-dimensional memory device includes a substrate, a plurality of horizontal conductive layers, a plurality of vertical memory structures and a vertical conductive post. The conductive layers are located above the substrate, and immediately-adjacent two of the conductive layers are spaced by a first air gap. The memory structures pass through the conductive layers and are connected to the substrate. The conductive post is located between immediately-adjacent two of the memory structures and passes through the conductive layers and is connected to the substrate. The conductive post is spaced from immediately-adjacent edges of the conductive layers by a second air gap.

Three dimensional memory device and method for fabricating the same

An ovonic threshold switch includes a first electrode, a second electrode, and an In-doped chalcogenide-based selector layer disposed between the first electrode and the second electrode, in which the In-doped chalcogenide-based selector layer has an In compound content of about 2 at. % to about 10 at. %. A memory cell including the In-doped chalcogenide-based selector layer is also provided.

Semiconductor device and memory cell

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Elmsford, NY, United States of America

Hsiang-Lan Lung