United Microelectronics Corp.

Hsiang-Hung Peng

Ching-Wen Hung

Chih-Sen Huang

Chun-Lung Chen

Sheng-Yuan Hsueh

Yi-Chung Sheng

Kun-Yuan Liao

Chia-Lin Lu

Chih-Kai Kang

Wei-Hao Huang

Shu-Hung Yu

Kuo-Yu Liao

Hung-Hsu Lin

Chih-Chien Liu

Yu-Fang Chien

Tsuoe-Hsiang Liao

Huo-Tieh Lu

A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

Mark pattern in semiconductor device

A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.

Semiconductor device

A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

Semiconductor device and fabrication method thereof

A three-dimensional conductive structure has a first electrode and a second electrode of a capacitor structure, and thereby defines a capacitor space. At least a signal line is further included in the capacitor space where both the first electrode and the second electrode can cross and detour round the signal line. Therefore, the signal line can go directly through the capacitor space for transferring various signals without making a detour to avoid the whole capacitor structure.

Conductive structure having capacitor

Growing community of inventors

Hsinchu County, Taiwan

Hsiang-Hung Peng