Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiang Hsiang Ko

Ying-Lang Wang

Miao-Cheng Liao

Wen Chu Hsiao

Ying Min Chou

You-Hua Chou

Min Hao Hong

Lai Wan Chong

Chun-Chieh Wang

Jian-Shin Tsai

Shiu-Ko JangJian

Ju Wen Hsiao

Kei-Wei Chen

Chen-Ming Huang

Chih-Tsung Lee

Hung Jui Chang

Jinn-Kwei Liang

Wen-Chieh Hsieh

Hsien-Wei Lin

Yi Ming Chen

A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate. The semiconductor device further includes a silicide layer over the first source/drain feature. The semiconductor device further includes a dielectric layer along the exposed portion of the isolation feature below the top surface of the substrate, wherein the dielectric layer contacts the silicide layer. The semiconductor device further includes a second source/drain feature in the substrate on an opposite side of a gate stack from the first source/drain feature, wherein the second source/drain feature has a substantially uniform thickness.

Semiconductor device

A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration.

Semiconductor devices utilizing partially doped stressor film portions

The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.

Reverse damascene process

A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.

Apparatus and method for reducing dark current in image sensors

A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.

A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.

Surface tension modification using silane with hydrophobic functional group for thin film deposition

A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.

Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same

In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer.

Method of manufacturing semiconductor device

An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

Two-step shallow trench isolation (STI) process

A method of making a device. The method comprises providing a first layer including a first material on a surface of a substrate, removing a portion of the first layer and a corresponding portion of the substrate to form an opening in the first layer and a recessed portion in the surface of the substrate, and supplying a liquid mixture to the opening and the recessed portion. The liquid mixture includes a first component having a first chemical affinity to the first material and a second component having a second chemical affinity to the first material, which is smaller than the first chemical affinity. The method also includes removing the second component and forming a second layer including the first component. The second layer covers the recessed portion and adheres to an edge portion of the first layer, such that the second layer and the recessed portion define a cavity.

Devices having a cavity structure and related methods

A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

Growing community of inventors

Sinying, Taiwan

Hsiang Hsiang Ko