Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiang-Ho Chang

Keh-Jeng Chang

Wen-Hao Chen

Hung-Chih Ou

Kuo-Fu Lee

Ke-Ying Su

Hui-I Wu

Wan-Ting Lo

Niranjan Vepuri

Po-Hsiang Huang

Yi-Kan Cheng

Sheng-Hsiung Chen

Fong-yuan Chang

Chin-Chou Liu

Chin-Her Chien

Cheng-Hung Yeh

Aftab Alam Khan

A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Semiconductor process technology assessment

An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.

Interposer with capacitors

Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.

RC tool accuracy time reduction

Growing community of inventors

Miaoli County, Taiwan

Hsiang-Ho Chang