United Microelectronics Corp.

Hsiang-Chieh Yen

Jian-Feng Li

Chia-Hua Chang

Yen-Chen Chen

Kuo-Chih Lai

Nien-Ting Ho

Shih-Min Chou

Yang-Ju Lu

Ching-Yun Chang

Chi-Mao Hsu

Yun-Tzu Chang

Min-Chuan Tsai

Zhi Jian Wang

Yun Tzu Chang

Fang-Yi Liu

Hsu-Sheng Huang

Jia Fang Wu

A high electron mobility transistor includes a substrate having a continuous planar front surface, a first epitaxial layer directly and continuous disposed on the continuous planar front surface of the substrate, a plurality of first recesses arranged in an upper portion of the first epitaxial layer, a second epitaxial layer directly disposed on the first epitaxial layer and partially filling the first recesses and surrounding a plurality of first air slits in the first recesses, a third epitaxial layer disposed on the second epitaxial layer, and a gate disposed on the third epitaxial layer.

Semiconductor device and method for forming the same

The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

Fabricating method of semiconductor device

Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.

Multiple-level interconnect structure and manufacturing method thereof

A high electron mobility transistor (HEMT) is disclosed. The HEMT includes a substrate, a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, a third epitaxial layer disposed on the second epitaxial layer, and a gate disposed on the third epitaxial layer. An upper portion of the first epitaxial layer has a plurality of first recesses. The second epitaxial layer partially fills the first recesses and surrounding a plurality of first air slits in the first recesses.

Semiconductor device and fabricating method thereof

A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Method for modulating work function of semiconductor device having metal gate structure by gas treatment

The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S) providing a substrate having a metal gate structure on a side of the substrate, (S) forming a titanium nitride (TiN) layer on the side of the substrate, and (S) performing a gate annealing to tune work function of the metal gate structure.

Method for tuning metal gate work function before contact formation in fin-shaped field effect transistor manufacturing process

A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

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Penghu County, Taiwan

Hsiang-Chieh Yen