Mstar Semiconductor, Inc.

Hsian-Feng Liu

Chun-Chia Chen

Chung-Ching Chen

Eer-Wen Tyan

Sterling Smith

Yu-Lin Chen

Ming-Chieh Yeh

Chao-An Chen

Yo-Lin Chen

Jiunn-Yih Lee

Ke-Chiang Huang

Meng-Tse Weng

Chun-Wen Yeh

Kuo-Feng Hsu

Yao-Zhong Zhang

Kai-Fei Chang

Hsin-Kuang Chen

Chieh-Wen Lee

A control method for a delay locked loop includes: delaying an input signal to generate an internal signal; delaying the internal signal to generate an output signal; and selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.

Delay locked loop and associated control method

A signal transmission method suitable for a signal transmitter includes: providing a plurality of clock signals with different phases, selecting some of the clock signals as a plurality of intermediate signals; transmitting the intermediate signals to a signal output circuit via a clock distribution network; selecting one of the intermediate signals as a reference clock of the signal output circuit to output data.

Data transmission method and associated signal transmitter

An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors. The first and second first-type transistors are commonly controlled by a first logic signal. The third first-type transistor is connected in parallel to the second first-type transistor. The pull-down circuit includes first, second and third second-type transistors. The first and second second-type transistors are commonly controlled by a second logic signal. The third second-type transistor is connected in parallel to the second second-type transistor. The pull-up circuit is configured such that a response speed of the first first-type transistor to the first logic signal is lower than that of the second first-type transistor to the first logic signal.

Output apparatus, output driver, and level shifting system

A driving circuit includes a first driving module, configured to operate at a first operating voltage in a first mode and configured to be deactivated in a second mode; and a second driving module, wherein at least part of the second driving module operates at a protection voltage in the first mode and operates at a second operating voltage in the second mode, wherein the second operating voltage and the protection voltage are lower than the first operating voltage.

Driving circuit and driving method

A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.

Control method and controller for DRAM

A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship.

Built-in self-test circuit applied to high speed I/O port

A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Apparatus and method of generating universal memory I/O

A transmitter comprises a protection circuit; a first termination resistor having a first end coupled to a first voltage source, and a second end coupled to the protection circuit; a second termination resistor having a first end coupled to the first voltage source, and a second end coupled to the protection circuit, wherein the second end of the first termination resistor and the second end of the second termination resistor form a differential output pair; a current switch coupled to the protection circuit; a current source coupled to the current switch; and a pre-driver circuit coupled to the current switch, for controlling the current switch, making the differential output pair generate an output current. Wherein, the pre-driver circuit receives a second voltage source, and the first voltage source is higher than the second voltage source.

Low voltage transmitter with high output voltage

A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.

Memory controller and associated control method

A phase generating apparatus generates an output clock having a desired phase according to a digital signal. The apparatus includes a phase selecting unit and a phase generating unit. The phase selecting unit selects one of a plurality of input clocks according to a portion of bits of the digital signal to generate a reference clock. Each of the input clocks respectively has a difference phase. The phase selecting unit divides the frequency of the reference clock, and selectively delays the frequency-divided reference clock according to another portion of bits of the digital signal to generate the output clock.

Phase generating apparatus and method thereof

A universal IO unit applied to a chip or an integrated circuit is provided. The universal IO unit includes a power pad and a plurality of signal pads for providing different functions. According to functional requirements of the universal IO unit, the pad power is selectively connected to an electric wire to couple to a predetermined voltage, and each of the signal pads is also selectively connected to a signal wire to transceive signals.

Universal IO unit, associated apparatus and method

A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes. The device comprises: a programmable equalizer, having a plurality of equalizing modes, receiving an original signal so as to output an equalized signal; a phase-locked loop, receiving a reference clock signal and a first control signal so as to output first sampling pulses and second sampling pulses; a data slicing device, coupled to the phase-locked loop and the programmable equalizer and receiving the first sampling pulses, the second sampling pulses and the equalized signal so as to output a first slicing signal and a second slicing signal; and a signal processing device, coupled to the data slicing device and receiving the first slicing signal and the second slicing signal so as to output the first control signal and a second control signal; wherein the signal processing device programs the programmable equalizer by using the second control signal so as to select an equalizing mode from the plurality of equalizing modes for the programmable equalizer.

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Hsinchu Hsien, Taiwan

Hsian-Feng Liu