Winbond Electronics Corporation

National Science Council of Republic of China

Hsi-Yuan Wang

Che-Min Lin

Jieh-Tsorng Wu

Li-Te Wu

Chun-Nan Li

Hen-Kai Chang

Chung-Wen Kao

Chih-Chieh Chuang

Te-Tsoung Tsai

Chiu Jui Ta

Jui-Ta Chiu

A refresh control circuit includes a clock signal generator, a plurality of pulse number adjusters and a plurality of address counters. The clock signal generator generates a clock signal. The pulse number adjusters receive the clock signal, and during a time period, respectively generate a plurality of adjusted clock signals by adjusting pulse number of the clock signal according to a plurality of data retention information. The address counters respectively generate a plurality of refresh address information according to the adjusted clock signals. The refresh address information respectively correspond to a plurality of memory banks of a memory device. The memory banks respectively perform refresh operations according to the refresh address information.

Refresh control circuit

A memory storage apparatus having a plurality of operating modes is provided. The memory storage apparatus includes a memory control circuit and a memory cell array circuit. The memory control circuit controls the memory storage apparatus to operate in one of the operating modes. The memory control circuit controls the memory storage apparatus to operate in a first operating mode and controls the memory storage apparatus to switch from the first operating mode to a second operating mode to refresh storage data of the memory cell array circuit. The memory storage apparatus operates in a third operating mode to refresh storage data in the memory storage apparatus. An operating voltage of the memory storage apparatus operating in the second operating mode is smaller than an operating voltage of the memory storage apparatus operating in the third operating mode.

Memory storage apparatus and operating method with multiple modes for refresh operation

A method and an apparatus in a computer system for connecting buses with different clock frequencies are provided. The method comprises receiving a request transmitted from a master to a slave. If the clock frequency of the master is lower than that of the slave such that the slave sees more requests than the master does, redundant cycles of the request signal are masked lest the slave repeatedly receive the request. The request is then transferred to the slave. If the clock frequency of the master is higher than that of the slave such that the slave cannot receive the request in time, then the request signal is lengthened so that the request signal is synchronized with the clock cycles of the slave. The output data responded from the slave is then transferred to the master.

Method and apparatus for connecting buses with different clock frequencies by masking or lengthening a clock cycle of a request signal in accordance with the different clock frequencies of the buses

The present invention provides a control circuit with multiple power sources, which accepts an output signal from a comparator circuit. This control circuit with multiple power sources contains two components: one is a voltage transferring circuit, which connects to the comparator and accepts the first and the second input voltages to react the controls of respective output signals for generating the first voltage potential and the second voltage potential; another is an output circuit, which connects to the voltage transferring circuit to react the controls of the first voltage potential and the second voltage potential for deciding the correct output from the first input voltage or the second input voltage.

Control circuit with multiple power sources

The differential comparator circuit for receiving an input voltage within a pre-determined range, amplifying the input voltage, and outputting an output voltage is provided. The circuit includes: a first differential comparator for receiving the input voltage within a first range portion of the range, amplifying the input voltage within the first range portion, and outputting the output voltage, a detecting circuit electrically connected to the first differential comparator, wherein a trigger signal is produced by the detecting circuit when the first differential comparator is shut down and is detected by the detecting circuit, and a second differential comparator electrically connected to the detecting circuit for receiving the input voltage within a second range portion of the range, amplifying the input voltage within the second range portion, and outputting the output voltage in response to the trigger signal.

Dual differential comparator circuit with full range of input swing

A digital FM demodulator utilizes delay lines as the timing reference and incorporates the concept of delta-sigma analog-to-digital conversion to implement the function of time-to-digital conversion. The FM demodulator is constructed from delay lines, a multiplexer, a phase detector, a charge pump circuit, a quantizer and a digital integrator. The modulated signal on an intermediate frequency carrier passes through the delay lines and is then phase-compared with the original modulation signal. The comparison produces a pulse which is converted into a voltage and stored in a capacitor by way of the charge pump circuit. The voltage having been accumulated and quantized, a new delayed output signal is acquired to compare its phase with the input signal. Meanwhile, the phase difference between input signal and delayed signal is used to select a delay for the delayed signal for the next cycle. The phase difference is continuously evaluated and adjusted to produce zero phase difference. The digital modulation signal is collected at the system output.

Digital FM demodulator with reduced quantization noise

A differential output driver device for receiving a differential input voltage within a specific range having a first portion of a relatively higher voltage and a second portion of a relatively lower voltage and obtaining an identical voltage variation for output voltages of the first portion and the second portion is provided. The differential output driver device includes a step-down circuit for receiving the first portion of the relatively higher voltage and lowing the relatively higher voltage to a first output voltage, a step-up circuit for receiving the second potion of the relatively lower voltage and rising the relatively lower voltage to a second output voltage, a first compensation circuit electrically connected to the step-down circuit for providing a first bias to transform the first output voltage into a first compensation voltage, and a second compensation circuit electrically connected to the step-up circuit for providing a second bias to transform the second output voltage into a second compensation voltage, wherein the second compensation voltage and the first compensation voltage have the identical voltage variation value, so as to make the driver generate a periodic output voltage having a substantially regular waveform.

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Hsinchu, Taiwan

Hsi-Yuan Wang