Winbond Electronics Corporation

Hsi-Hsien Hung

Johnny Chan

Seow Fong Lim

Dennis Cheng

A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.

Memory device and control method thereof

A memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines extending in a row direction and coupled to respective rows of the memory cells, and a plurality of local bit lines extending in a column direction and coupled to respective columns of the memory cells. The control unit is configured to program a selected one of the rows of memory cells to have a predetermined pattern of digital states, couple selected ones of the local bit lines to a global bit line and couple unselected ones of the local bit lines to ground based on the predetermined pattern, apply a stress voltage to the global bit line, and after a predetermined period of time, sense the digital states of the selected row of memory cells.

Memory device and stress testing method of same

The invention provides a semiconductor wafer with a die area and a scribe area, and the semiconductor wafer includes a die and a testing circuit. The die is formed on the die region of the semiconductor wafer, and the die includes a main circuit. The testing circuit is disposed on the scribe area of the semiconductor wafer, and is electrically connected to the die for testing the main circuit.

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Palo Alto, CA, United States of America

Hsi-Hsien Hung