Vanguard International Semiconductor Corporation

Winbond Electronics Corporation

Other

Windbond Electronics Corp.

Hsi-Chuan Chen

Jung-Ho Chang

Dahcheng Lin

Kuo-Shu Tseng

Sen-Huan Huang

Bor-Ru Sheu

Haochieh Liu

Hong-Hsiang Tsai

Shye-Lin Wu

Ming-Hong Kuo

Li-Ming Wang

Wen-Kuei Hsieh

Wen-Kuei Huang

Tien-Jen Chen

A real-time insulation detector for feeding a high-frequency low-voltage signal is electrically connected with a power system, and the power system includes a power circuit comprised of a main power circuit and plural branch circuits, a plurality of power transformers are arranged in the main power circuit and the plural branch circuits, and each current power transformer has a positive electrode point and a negative electrode point arranged on a low-voltage side thereof, the real-time insulation detector contains a central controller, a signal generator, a circuit selector, a plurality of detection circuits, plural first safety circuits, and plural second safety circuits. Thereby, the real-time insulation detector automatically feeds a high-frequency low-voltage detection signal, and when the power system runs in an uninterruptible power network, the central controller judges aging insulation comes from which one cable or component of the power system.

Real-time insulation detector for feeding high-frequency low-voltage signal of power system

Low leakage and low resistance plugs for a memory device and the manufacturing method for the plugs includes a doped polysilicon layer first deposited at contact nodes and bit-line contacts inside the memory to form a low leakage interface. A low contact resistance imbedded tungsten plug is subsequently deposited on the polysilicon layer to form a low contact resistance imbedded tungsten plug in concavities at the contact nodes and bit-line contacts. Excess material is etched to leave double layer plugs at the contact nodes and bit-line contacts that constitute low leakage and low contact resistance memory plugs.

Low leakage and low resistance for memory and the manufacturing method for the plugs

A method of fabricating a trench capacitor includes forming a trench in a substrate; forming a conductive diffusion region in the substrate surrounding a lower portion of the trench; forming a dielectric layer along an inner surface of the trench; and filling the trench with a first doped polysilicon layer. A first recess is formed to expose an upper portion of the inner sidewall of the trench. A collar dielectric layer is formed on the exposed inner sidewall. The first recess is filled with a second doped polysilicon layer. A second recess is formed to expose a part of the upper portion of the inner sidewall. A gap is formed between the exposed inner sidewall and the second doped polysilicon layer, and filled with a doped polysilicon layer converted from an undoped polysilicon layer.

Method of fabricating deep trench capacitor

A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.

Method of manufacturing DRAM capacitor

A fabrication method for a self-aligned contact opening involves using polysilicon to protect a cap layer above a conductive line or even a corner of a spacer on a sidewall of the conductive line. A silicon oxide layer is then etched using a conventional silicon oxide etching recipe to form a self-aligned contact opening. This conventional silicon oxide etching recipe not only has a higher etching selectivity for silicon oxide to silicon nitride, but also yields a higher etching selectivity ratio for silicon oxide to polysilicon.

Method of fabricating a self-aligned contact opening

A method of creating a DRAM capacitor structure, featuring a crown shaped storage node structure, has been developed. The crown shaped storage node structure, features the formation of an hemispherical grain, (HSG), silicon layer, only on a top portion of the structure, with the bottom portion of the crown shaped storage node structure, featuring non - HSG, or smooth surfaces. This configuration is achieved via creation of a capacitor opening, in a doped oxide - undoped oxide, composite insulator layer, used as the shape for subsequent formation of an amorphous silicon crown shaped structure. Selective removal of the overlying doped oxide layer, allows selective formation of an HSG silicon layer, only on the exposed top portion of the amorphous silicon crown shaped structure. Subsequent removal of the undoped oxide layer, exposes a bottom portion of the amorphous silicon crown shaped structure, featuring non - HSG silicon surfaces, allowing easier formation of a capacitor dielectric layer, specifically at the bottom corner of the crown shaped storage node structure.

Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure

A method of fabricating a semiconductor device having a landing plug is provided. First, a substrate is provided, which has active areas, wordlines stretching over the active areas and an isolation layer filling the gaps between the wordlines. Second, a pattern is defined and the isolation layer masked with the pattern is etched for the formation of bitline and node contacts, wherein the pattern has a protrusion which shortens the length of the bitline to wordline overlap formed thereby. Finally, the contacts are filled with a conducting layer.

Lading plug contact pattern for DRAM application

A process for creating a DRAM capacitor structure, featuring a doped polysilicon layer, overlying a crown shaped storage node electrode, has been developed. The process features the use of an HSG silicon layer, on a doped amorphous silicon, storage node shape, with the HSG silicon layer supplying increased surface area, and thus increased capacitance, for the DRAM capacitor. A doped polysilicon layer, selectively deposited on the underlying HSG silicon layer, supplies additional dopant to the HSG silicon layer, residing on the doped amorphous silicon, storage node shape, thus minimizing a capacitance depletion phenomena, that can be present with lightly doped storage node structures.

Method to decrease capacitance depletion, for a DRAM capacitor, via

A method for insitu forming a SiN layer and an overlying Silicon oxynitride layer in one chamber. A substrate is loaded into a chamber. The substrate has thereover a polysilicon layer and a overlying metal layer. In a first in-situ step, a nitride layer is deposited using a LPCVD process over the substrate. The nitride layer is preferably formed at a temperature between 650 and 800.degree. C. and flowing SiH.sub.2 Cl.sub.2 and NH.sub.3. In a second in-situ step, an oxynitride layer is deposited over the nitride layer. The oxynitride layer acts as a bottom anti-reflective coating (BARC). The oxynitride (SiON) layer can be formed by a LPCVD process. Second, the LPCVD oxynitride can be formed a temperature between 600 and 800.degree. C. with a SiH.sub.4 flow and a N.sub.2 O flow. The substrate is removed from the chamber. A photoresist layer is formed over the oxynitride layer. The photoresist layer is exposed using the oxynitride layer as a bottom anti-reflective coating (BARC). The photoresist layer is developed. The oxynitride layer, the nitride layer, the metal layer and the polysilicon layer are etched to form a gate structure. The gate structure has sidewalls. Spacers are formed on the sidewalls of the gate structure. An ILD layer is formed over the gate structure. A contact hole is etched through the ILD layer using the gate structures and spacers as a mask to expose the substrate to form a self aligned contact (SAC) opening.

In-situ nitride and oxynitride deposition process in the same chamber

A process for creating a DRAM capacitor structure, comprised of a storage node electrode, featuring an HSG silicon layer, on the surface of the storage node electrode, used to increase capacitor surface area, has been developed. The process features the use of a UHV system, allowing: a pre-clean procedure; an HSG seeding procedure; an anneal procedure used to create an HSG silicon layer; and a silicon nitride deposition; all to be performed in situ, without exposure to air, thus removing, and avoiding, unwanted native oxide layers. This invention allows a nitride--oxide, capacitor dielectric layer, to be formed in situ, in the UHV system, on an underlying storage node electrode structure, which in turn experienced in situ procedures, in the UHV system, resulting in HSG silicon layer, formed after an in situ, pre-clean, an HSG silicon seeding procedure, and an anneal procedure.

In situ, one step, formation of selective hemispherical grain silicon

An improved and new process for fabricating planarized isolation trenches, wherein sharp corners at the top periphery of the trench are eliminated and erosion of insulating material at the edges of isolation trenches is suppressed, has been developed. The process uses a two layer mask to etch the isolation trench, followed by an isotropic etch to recess the first layer of the mask. An oxide liner is formed in the trench and across the exposed edge of the trench resulting in rounding the corners of the trench. Then, a second isotropic etch is used to recess the edge of the second mask layer, so that its opening now is beyond the edge of the trench. An oxide layer is conformally deposited over all exposed surfaces and fills the trench. After CMP to planarize the oxide layer, the remaining oxide fills the trench and, also, extends a small distance beyond the edge of the trench and serves to protect edge of the trench during subsequent etching.

Process for recess-free planarization of shallow trench isolation

A process for creating a storage node electrode for a DRAM capacitor structure, featuring increased surface area accomplished using an HSG silicon layer as the top layer for the storage node electrode, has been developed. The process features the use of a composite buffer layer of undoped and lightly doped amorphous silicon layers, located overlying a heavily doped amorphous silicon layer, and then followed by the deposition of HSG silicon seeds. A first anneal cycle then allows formation of an undoped HSG silicon layer to be realized on the underlying heavily doped amorphous silicon layer, via consumption of the HSG seeds, and of the composite buffer layer of undoped and lightly doped amorphous silicon layers. A second anneal cycle then allows dopant from the underlying heavily doped amorphous silicon layer to reach the undoped HSG silicon layer, resulting in a doped HSG silicon layer. Patterning, or CMP, of the doped HSG silicon layer, and of the heavily doped amorphous silicon layer, results in the creation of a storage node electrode. The use of the composite buffer layer allows the growth of an undoped HSG silicon layer to be achieved, thus maximizing uniformity and HSG silicon roughness, while the anneal cycle, applied to the undoped HSG silicon layer, results in the attainment of the doped HSG silicon layer, offering reduced capacitance depletion compared to undoped HSG silicon counterparts.

Growth enhancement of hemispherical grain silicon on a doped polysilicon

A process for creating a crown shaped storage node electrode, covered with an HSG silicon layer, used to increase the surface area, and thus the capacitance of, high density, DRAM designs, has been developed. The process features creating a crown shaped storage node shape, from a composite amorphous silicon layer, wherein the composite amorphous silicon layer is comprised of a heavily doped amorphous silicon layer, used to alleviate capacitance depletion phenomena, sandwiched between undoped, or lightly doped, amorphous silicon layers, used to selectively accept the overlying HSG silicon layer. The process also features the use an HF vapor pre-clean procedure, followed by an in situ, selective deposition of HSG silicon seeds, in a conventional LPCVD chamber, prior to anneal cycle used to form the HSG silicon layer.

One step in situ doped amorphous silicon layers used for selective

A process for creating an insulator filled, shallow trench isolation region, in a semiconductor substrate, has been developed. The process features the use of a high temperature hydrogen anneal, performed after an anisotropic RIE procedure, used to create the shallow trench shape, in the semiconductor substrate. The high temperature hydrogen anneal procedure repairs defects in the semiconductor substrate, created by the shallow trench, RIE procedure, and also creates a denuded zone, at or near the shallow trench shape, exposed silicon surface. The defect free denuded zone allows the formation of a uniform insulator trench liner to be realized, and also allows a minimum of junction leakage to occur at the region in which a source/drain-substrate junction, is butted against the side of the insulator filled, shallow trench.

Process to reduce defect formation occurring during shallow trench

A method for creating a stacked, or crown shaped, capacitor structure, with increased surface area, obtained using a storage node electrode, comprised of HSG silicon grains on the surface of the storage node electrode, has been developed. An in situ procedure, allows HSG silicon seeds to be selectively formed, only on the exposed surfaces of a amorphous silicon storage node electrode shape, in an LPCVD system, directly after an HF preclean step. A subsequent anneal, again performed in situ, in the LPCVD system, results in the formation of HSG silicon grains, converted from the HSG silicon seeds.

Growing community of inventors

Tainan, Taiwan

Hsi-Chuan Chen