Novatek Microelectronics Corp.

Hsi-Chi Ho

Kuei-Chung Chang

Feng-Jung Kuo

Li-Chun Huang

Yu-Hsun Peng

Ching-Wen Lai

Wei-Ying Tu

A drive circuit applicable to a display device includes a first signal path and a second signal path. The first signal path, configured to receive and transmit image data, includes a compression unit configured to perform a compression procedure on the image data to generate compression data; a storage unit configured to store the compression data; and a de-compression unit configured to perform a de-compression procedure on the compression data to recover the image data. The second signal path is configured to transmit the image data to the storage unit so as to bypass the compression unit, and transmit the image data received from the storage unit to a display unit so as to bypass the de-compression unit when the image data is not transmitted by the first signal path. The received image data is passed through the first signal path or the second signal path depending upon its characteristics.

Data compression system for liquid crystal display and related power saving method

A drive circuit applicable to a display device includes a first signal path and a second signal path. The first signal path, configured to receive image data and transmit the image data in a first operation mode, includes a compression unit, a storage unit and a de-compression unit. In the first operation mode, the compression unit performs a compression procedure on the image data to generate compression data, the storage unit stores the compression data, and the de-compression unit receives the compression data and performs a de-compression procedure on the compression data to recover the image data. The second signal path is configured to receive image data, transmit the image data to the storage unit so as to bypass the compression unit, and transmit the image data received from the storage unit to a display unit so as to bypass the decompression unit in a second operation mode.

A data compression system for a liquid crystal display (LCD) includes a host and a drive circuit. The host is utilized for outputting image data in a first data format or a second data format according to an operation mode of the LCD. The drive circuit includes a bypass path, for transmitting the image data according to the operation mode; a compression unit, coupled to the host, for receiving the image data and performing a compression procedure on the image data to generate a compression data according to the operation mode; a storage unit, coupled to the compression unit, for storing the compression data and the image data; a de-compression unit, coupled to the storage unit, for receiving the compression data and performing a de-compression procedure on the compression data to recover the image data according to the operation mode; and a display unit, for displaying the image data.

A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N&#xd7;M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N&#xd7;M arbiters, generates N&#xd7;M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N&#xd7;M arbiters to sequentially control the N&#xd7;M arbiters.

Memory architecture for display device and control method thereof

A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on.

Data driver and multiplexer circuit with body voltage switching circuit

A data transmission detecting device including a detecting module and a detection value calculating module is provided. The detecting module has a plurality of receiving terminals and receives a first data and a second data during a first period. The detecting module calculates a total detection value according to the first data and the second data, and performs an error check comparison by comparing the total detection value with an error check code. When the detecting module again receives the first data during a second period, the detection value calculating module transmits an auxiliary detection value to the detecting module, so that the detecting module calculates a corresponding total detection value according to the auxiliary detection value, and performs the error check comparison by comparing the total detection value with the error check code. The first period and the second period are two successive periods adjacent to each other.

Data transmission detecting device, data transmission detecting method and electronic device thereof

A motion detection method is adapted for an image display circuit including a motion detection circuit and an arbitration circuit. In this motion detection method, a number of motion quality observation windows are defined. Each motion quality observation window includes a start point and an ending point. In the motion quality observation windows, a write frame count value is adjusted according to a write frame command. At the end point of each motion quality observation window, if the write frame count value is equal to or bigger than a preset count value, an enable signal is outputted to the arbitration circuit to determine whether the image display circuit performs motion display. In the motion quality observation windows, the end point of the i-th motion quality observation window is located between the start point and the end point of the (i+1)-th motion quality observation window, where i is a positive integer.

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Hsinchu, Taiwan

Hsi-Chi Ho