Marvellworld Trade Ltd.

Marvell International Limited

Intel Corporation

Hsi-Cheng Chu

Jack Kang

Yu-Chi Chuang

Dishi Lai

Kanting Tsai

Chun-Lun Lin

Robert G Southworth

Chih-Jen Chang

Naru Dames Sundar

Technologies for managing exact match hash table growth include a network computing device which includes a compute engine and a network interface controller (NIC). The NIC is configured to allocate a plurality of physical bucket addresses in non-contiguous chunks of memory of the compute engine, configure a bucket threshold value as a function of a hash size of the hash table, generate a plurality of virtual bucket addresses as a function of the bucket threshold value, and map each generated virtual bucket address to an allocated physical bucket address. Other embodiments are described herein.

Technologies for managing exact match hash table growth

A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate with a storage device via a second interface. The second interface is separate from the first interface. The bridge module is configured to allow the controller to transfer data between the storage device and the host without buffering the data, and to access a memory of the host via the first interface during the transfer.

Bridge between two different controllers for transferring data between host and storage device

A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.

Disabling threads in multithread environment

A system including a first controller configured to communicate with a host via a first interface; a second controller configured to communicate with a storage device via a second interface, where the second interface is different than the first interface; and a bridge module configured to allow the second controller to transfer data between the storage device and the host and to allow the second controller to access memory of the host via the first interface during the transfer.

USB-to-SATA high-speed bridge

A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread. The method additionally includes resetting the cycle counts when a master instruction execution thread is in the active mode.

Methods and apparatus for handling switching among threads within a multithread processor

Multithread handling

Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.

Interrupt handling

A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread. The method additionally includes resetting the cycle counts when a master instruction execution thread is in the active mode. Other embodiments may be described and claimed.

A system, apparatus and method for interrupt handling on a multi-thread processing device are described herein. Embodiments of the present invention provide a multi-thread processing device for interrupt handling including an interrupt block to provide interrupt signals to a fetch block, including a first interrupt signal line corresponding to a first instruction execution thread and a second interrupt signal line corresponding to a second instruction execution thread. In embodiments, the multi-thread processing device may handle interrupts by providing a shared interrupt service routine for multiple threads or by providing each thread its own unique interrupt service routine.

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San Jose, CA, United States of America

Hsi-Cheng Chu