Macronix International Co., Ltd.

Holtek Semiconductor Corp.

Hsan-Fong Lin

Chi-Ho Hsu

Chi-Bing Chen

Jhy-Rong Chen

Wen-Fu Yang

Chia-Lu Hsu

A circuit capable of providing stable timing clock includes: a step-down clamping circuit, an oscillating circuit, and a voltage potential-conversing circuit. The step-down clamping circuit that step down the input first voltage potential, and clamp to output second voltage, the oscillating circuit is coupled to the clamping circuit and is an oscillating circuit that takes the second voltage as a operating voltage to generate a first timing clock signal, which has a lower voltage potential. The voltage potential-conversing circuit is coupled to the oscillating circuit to convert the first timing clock signal into a second timing clock signal, which has a higher voltage potential. And it is a stable timing clock signal available for other system circuit.

Stable timing clock circuit

A pulse shaper for integrated service digital network (ISDN) U-interface. The pulse shaper of the present invention includes a couple of control clock generators, a clock-controlled fully differential switched-capacitor integrator, a fully differential sample and hold circuit, and a fully differential line driver/Rauch lowpass filter. The pulse shaper converts four-level 2B1Q digital input code (D0 and D1) to five staircase-type analog waveform by using fully differential switched-capacitor integrator. The sample and hold circuit then eliminates the spikes in the five-stair waveform and improve the signal linearity. The lowpass filter and telephone line driver is utilized to perform the output signal to comply with the waveform specification of ANSI T1 5.3.2.1 and 5.3.2.2.

Pulse shaper apparatus and method for ISDN U-interface

Growing community of inventors

Hsinchu, Taiwan

Hsan-Fong Lin