Texas Instruments Corporation

Raytheon Company

Hrishikesh Shinde

Steven Derrick Clynes

Daryl Coleman

Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.

Circuit implementation in resource constrained systems

A video display system, such as useful in video surveillance applications, is disclosed. The system includes a video decoder () having a common output data port () at which it presents interleaved data streams (DSA, DSB). The interleaved data streams (DSA, DSB) may correspond to multiple scalings of a processed video input signal, for example as received from a surveillance camera (C, C, C, C). The video decoder () also outputs multiple clock signals (CLKA, CLKB), each of which are synchronous with a corresponding one of the interleaved data streams (DSA, DSB). This enables a common data port () to output multiple data streams (DSA, DSB), while individual destinations (A,B) of the data streams (DSA, DSB) can continue to operate at legacy clock rates.

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Dallas, TX, United States of America

Hrishikesh Shinde