Microsoft Technology Licensing, LLC

HoYuen Chau

Robin Andrew Alexander

Xiaozhong Xing

Liang Yang

Vishal Jose Mannanal

Danyu Zhu

Albert Gordon Greenberg

Daniel Max Firestone

Pankaj Garg

Hoi Huu Vo

Yimin Deng

Steven J Pratschner

Bryan William Tuttle

Yue Zuo

Danny Chen

Jay Krell

Allan James Murphy

An I/O processing system includes reception of a request to perform an I/O operation from a user-mode application, providing of the request to a storage device, scheduling of an operating system deferred procedure call to determine whether the storage device has completed the I/O operation, execution of the scheduled deferred procedure call to determine that the storage device has completed the I/O operation, and transmission of a return corresponding to the completed I/O operation to the user-mode application.

I/O completion polling for low latency storage device

An I/O processing system includes reception of a request to perform an I/O operation at a storage driver, and, in response to receiving the request, providing of the request to a storage device, and scheduling a timer associated with a callback routine to determine whether the storage device has completed the I/O operation, and, in response to expiration of the scheduled timer, determination of whether the storage device has completed the I/O operation.

Timer-based I/O completion polling for low latency storage device

High-performance tracing can be achieved for an input program having a plurality of instructions. Techniques such as executable instruction transcription can enable execution of a plurality of instructions at a time via a run buffer. Execution information can be extracted via run buffer execution. Fidelity of execution can be preserved by executing instructions on the target processor. Other features, such as an executable extraction instruction ensemble, branch interpretation, and relative address compensation can be implemented. High quality instruction tracing can thus be achieved without the usual performance penalties.

High-performance processor instruction tracing

The present invention extends to methods, systems, and computer program products for offloading packet processing for networking device virtualization. A host maintains rule set(s) for a virtual machine, and a physical network interface card (NIC) maintains flow table(s) for the virtual machine. The physical NIC receives and processes a network packet associated with the virtual machine. Processing the network packet includes the physical NIC comparing the network packet with the flow table(s) at the physical NIC. When the network packet matches with a flow in the flow table(s) at the physical NIC, the physical NIC performs an action on the network packet based on the matching flow. Alternatively, when the network packet does not match with a flow in the flow table(s) at the physical NIC, the physical NIC passes the network packet to the host partition for processing against the rule set(s).

Offloading packet processing for networking device virtualization

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Bellevue, WA, United States of America

HoYuen Chau